riscv/rocket-chip
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Don't modulate PMP privilege on passsthrough when !usingVM

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This commit is contained in:
Andrew Waterman 2017-03-24 13:01:47 -07:00
parent 3f0d2fe826
commit 97006ab396
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/TLB.scala
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@ -93,7 +93,7 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
pmp.io.addr := mpu_physaddr pmp.io.addr := mpu_physaddr
pmp.io.size := io.req.bits.size pmp.io.size := io.req.bits.size
pmp.io.pmp := io.ptw.pmp pmp.io.pmp := io.ptw.pmp
pmp.io.prv := Mux(do_refill || io.req.bits.passthrough /* PTW */, PRV.S, priv) pmp.io.prv := Mux(Bool(usingVM) && (do_refill || io.req.bits.passthrough /* PTW */), PRV.S, priv)
val legal_address = edge.manager.findSafe(mpu_physaddr).reduce(_||_) val legal_address = edge.manager.findSafe(mpu_physaddr).reduce(_||_)
def fastCheck(member: TLManagerParameters => Boolean) = def fastCheck(member: TLManagerParameters => Boolean) =
legal_address && Mux1H(edge.manager.findFast(mpu_physaddr), edge.manager.managers.map(m => Bool(member(m)))) legal_address && Mux1H(edge.manager.findFast(mpu_physaddr), edge.manager.managers.map(m => Bool(member(m))))