From 97006ab396d9b0f9d3ad01ba8b468e49c8b42ac7 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 24 Mar 2017 13:01:47 -0700 Subject: [PATCH] Don't modulate PMP privilege on passsthrough when !usingVM --- src/main/scala/rocket/TLB.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/TLB.scala b/src/main/scala/rocket/TLB.scala index f9cb1aad..51f84459 100644 --- a/src/main/scala/rocket/TLB.scala +++ b/src/main/scala/rocket/TLB.scala @@ -93,7 +93,7 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters pmp.io.addr := mpu_physaddr pmp.io.size := io.req.bits.size pmp.io.pmp := io.ptw.pmp - pmp.io.prv := Mux(do_refill || io.req.bits.passthrough /* PTW */, PRV.S, priv) + pmp.io.prv := Mux(Bool(usingVM) && (do_refill || io.req.bits.passthrough /* PTW */), PRV.S, priv) val legal_address = edge.manager.findSafe(mpu_physaddr).reduce(_||_) def fastCheck(member: TLManagerParameters => Boolean) = legal_address && Mux1H(edge.manager.findFast(mpu_physaddr), edge.manager.managers.map(m => Bool(member(m))))