riscv/rocket-chip
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Merge branch 'master' into HEAD

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Scott Johnson
2016-08-22 11:37:30 -07:00
parent 75efc7dee7 8d6f080ed0
commit 96e2cefb34
3 changed files with 22 additions and 14 deletions
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vsim/Makefrag
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@ -45,7 +45,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
$(RISCV)/lib/libfesvr.so \
-sverilog \
+incdir+$(generated_dir) \
+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
+define+PRINTF_COND=$(TB).printf_cond \
+define+STOP_COND=!$(TB).reset \
+define+RANDOMIZE \