riscv/rocket-chip
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unittest: try both aFlow settings of TLToAHB

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This commit is contained in:
Wesley W. Terpstra 2017-03-16 15:13:57 -07:00
parent 604a164b97
commit 963d244094
2 changed files with 13 additions and 12 deletions
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20
src/main/scala/uncore/ahb/Test.scala
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@ -16,7 +16,7 @@ class RRTest1(address: BigInt)(implicit p: Parameters) extends AHBRegisterRouter
new AHBRegBundle((), _) with RRTest1Bundle)( new AHBRegBundle((), _) with RRTest1Bundle)(
new AHBRegModule((), _, _) with RRTest1Module) new AHBRegModule((), _, _) with RRTest1Module)
class AHBFuzzNative()(implicit p: Parameters) extends LazyModule class AHBFuzzNative(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
{ {
val fuzz = LazyModule(new TLFuzzer(5000)) val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel("AHBFuzzNative")) val model = LazyModule(new TLRAMModel("AHBFuzzNative"))
@ -25,7 +25,7 @@ class AHBFuzzNative()(implicit p: Parameters) extends LazyModule
val gpio = LazyModule(new RRTest0(0x100)) val gpio = LazyModule(new RRTest0(0x100))
model.node := fuzz.node model.node := fuzz.node
xbar.node := TLToAHB()(TLDelayer(0.1)(model.node)) xbar.node := TLToAHB(aFlow)(TLDelayer(0.1)(model.node))
ram.node := xbar.node ram.node := xbar.node
gpio.node := xbar.node gpio.node := xbar.node
@ -34,12 +34,12 @@ class AHBFuzzNative()(implicit p: Parameters) extends LazyModule
} }
} }
class AHBNativeTest()(implicit p: Parameters) extends UnitTest(500000) { class AHBNativeTest(aFlow: Boolean)(implicit p: Parameters) extends UnitTest(500000) {
val dut = Module(LazyModule(new AHBFuzzNative).module) val dut = Module(LazyModule(new AHBFuzzNative(aFlow)).module)
io.finished := dut.io.finished io.finished := dut.io.finished
} }
class AHBFuzzMaster()(implicit p: Parameters) extends LazyModule class AHBFuzzMaster(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
{ {
val node = AHBOutputNode() val node = AHBOutputNode()
val fuzz = LazyModule(new TLFuzzer(5000)) val fuzz = LazyModule(new TLFuzzer(5000))
@ -47,7 +47,7 @@ class AHBFuzzMaster()(implicit p: Parameters) extends LazyModule
model.node := fuzz.node model.node := fuzz.node
node := node :=
TLToAHB()( TLToAHB(aFlow)(
TLDelayer(0.2)( TLDelayer(0.2)(
TLBuffer(TLBufferParams.flow)( TLBuffer(TLBufferParams.flow)(
TLDelayer(0.2)( TLDelayer(0.2)(
@ -83,9 +83,9 @@ class AHBFuzzSlave()(implicit p: Parameters) extends LazyModule
} }
} }
class AHBFuzzBridge()(implicit p: Parameters) extends LazyModule class AHBFuzzBridge(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
{ {
val master = LazyModule(new AHBFuzzMaster) val master = LazyModule(new AHBFuzzMaster(aFlow))
val slave = LazyModule(new AHBFuzzSlave) val slave = LazyModule(new AHBFuzzSlave)
slave.node := master.node slave.node := master.node
@ -95,7 +95,7 @@ class AHBFuzzBridge()(implicit p: Parameters) extends LazyModule
} }
} }
class AHBBridgeTest()(implicit p: Parameters) extends UnitTest(500000) { class AHBBridgeTest(aFlow: Boolean)(implicit p: Parameters) extends UnitTest(500000) {
val dut = Module(LazyModule(new AHBFuzzBridge).module) val dut = Module(LazyModule(new AHBFuzzBridge(aFlow)).module)
io.finished := dut.io.finished io.finished := dut.io.finished
} }

5
src/main/scala/unittest/Configs.scala
View File

@ -12,8 +12,9 @@ class WithUncoreUnitTests extends Config((site, here, up) => {
implicit val p = q implicit val p = q
Seq( Seq(
Module(new uncore.tilelink2.TLFuzzRAMTest), Module(new uncore.tilelink2.TLFuzzRAMTest),
Module(new uncore.ahb.AHBBridgeTest), Module(new uncore.ahb.AHBBridgeTest(true)),
Module(new uncore.ahb.AHBNativeTest), Module(new uncore.ahb.AHBNativeTest(true)),
Module(new uncore.ahb.AHBNativeTest(false)),
Module(new uncore.apb.APBBridgeTest), Module(new uncore.apb.APBBridgeTest),
Module(new uncore.axi4.AXI4LiteFuzzRAMTest), Module(new uncore.axi4.AXI4LiteFuzzRAMTest),
Module(new uncore.axi4.AXI4FullFuzzRAMTest), Module(new uncore.axi4.AXI4FullFuzzRAMTest),