From 963d244094bf40d202958162a06f7e027c4a3ae9 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Thu, 16 Mar 2017 15:13:57 -0700
Subject: [PATCH] unittest: try both aFlow settings of TLToAHB

---
 src/main/scala/uncore/ahb/Test.scala  | 20 ++++++++++----------
 src/main/scala/unittest/Configs.scala |  5 +++--
 2 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/src/main/scala/uncore/ahb/Test.scala b/src/main/scala/uncore/ahb/Test.scala
index 6bcf94f7..43fbcb49 100644
--- a/src/main/scala/uncore/ahb/Test.scala
+++ b/src/main/scala/uncore/ahb/Test.scala
@@ -16,7 +16,7 @@ class RRTest1(address: BigInt)(implicit p: Parameters) extends AHBRegisterRouter
   new AHBRegBundle((), _)    with RRTest1Bundle)(
   new AHBRegModule((), _, _) with RRTest1Module)
 
-class AHBFuzzNative()(implicit p: Parameters) extends LazyModule
+class AHBFuzzNative(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
 {
   val fuzz  = LazyModule(new TLFuzzer(5000))
   val model = LazyModule(new TLRAMModel("AHBFuzzNative"))
@@ -25,7 +25,7 @@ class AHBFuzzNative()(implicit p: Parameters) extends LazyModule
   val gpio  = LazyModule(new RRTest0(0x100))
 
   model.node := fuzz.node
-  xbar.node := TLToAHB()(TLDelayer(0.1)(model.node))
+  xbar.node := TLToAHB(aFlow)(TLDelayer(0.1)(model.node))
   ram.node  := xbar.node
   gpio.node := xbar.node
 
@@ -34,12 +34,12 @@ class AHBFuzzNative()(implicit p: Parameters) extends LazyModule
   }
 }
 
-class AHBNativeTest()(implicit p: Parameters) extends UnitTest(500000) {
-  val dut = Module(LazyModule(new AHBFuzzNative).module)
+class AHBNativeTest(aFlow: Boolean)(implicit p: Parameters) extends UnitTest(500000) {
+  val dut = Module(LazyModule(new AHBFuzzNative(aFlow)).module)
   io.finished := dut.io.finished
 }
 
-class AHBFuzzMaster()(implicit p: Parameters) extends LazyModule
+class AHBFuzzMaster(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
 {
   val node  = AHBOutputNode()
   val fuzz  = LazyModule(new TLFuzzer(5000))
@@ -47,7 +47,7 @@ class AHBFuzzMaster()(implicit p: Parameters) extends LazyModule
 
   model.node := fuzz.node
   node :=
-    TLToAHB()(
+    TLToAHB(aFlow)(
     TLDelayer(0.2)(
     TLBuffer(TLBufferParams.flow)(
     TLDelayer(0.2)(
@@ -83,9 +83,9 @@ class AHBFuzzSlave()(implicit p: Parameters) extends LazyModule
   }
 }
 
-class AHBFuzzBridge()(implicit p: Parameters) extends LazyModule
+class AHBFuzzBridge(aFlow: Boolean)(implicit p: Parameters) extends LazyModule
 {
-  val master = LazyModule(new AHBFuzzMaster)
+  val master = LazyModule(new AHBFuzzMaster(aFlow))
   val slave  = LazyModule(new AHBFuzzSlave)
 
   slave.node := master.node
@@ -95,7 +95,7 @@ class AHBFuzzBridge()(implicit p: Parameters) extends LazyModule
   }
 }
 
-class AHBBridgeTest()(implicit p: Parameters) extends UnitTest(500000) {
-  val dut = Module(LazyModule(new AHBFuzzBridge).module)
+class AHBBridgeTest(aFlow: Boolean)(implicit p: Parameters) extends UnitTest(500000) {
+  val dut = Module(LazyModule(new AHBFuzzBridge(aFlow)).module)
   io.finished := dut.io.finished
 }
diff --git a/src/main/scala/unittest/Configs.scala b/src/main/scala/unittest/Configs.scala
index 5d6803d6..482e72bf 100644
--- a/src/main/scala/unittest/Configs.scala
+++ b/src/main/scala/unittest/Configs.scala
@@ -12,8 +12,9 @@ class WithUncoreUnitTests extends Config((site, here, up) => {
     implicit val p = q
     Seq(
       Module(new uncore.tilelink2.TLFuzzRAMTest),
-      Module(new uncore.ahb.AHBBridgeTest),
-      Module(new uncore.ahb.AHBNativeTest),
+      Module(new uncore.ahb.AHBBridgeTest(true)),
+      Module(new uncore.ahb.AHBNativeTest(true)),
+      Module(new uncore.ahb.AHBNativeTest(false)),
       Module(new uncore.apb.APBBridgeTest),
       Module(new uncore.axi4.AXI4LiteFuzzRAMTest),
       Module(new uncore.axi4.AXI4FullFuzzRAMTest),