riscv/rocket-chip
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Report ITIM slave port errors to BusErrorUnit

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This commit is contained in:
Andrew Waterman 2017-11-06 12:39:17 -08:00
parent c84848afa6
commit 95d00b13cc
1 changed files with 5 additions and 4 deletions
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9
src/main/scala/rocket/ICache.scala
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@ -273,12 +273,13 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
val s1_scratchpad_hit = Mux(s1_slaveValid, lineInScratchpad(scratchpadLine(s1s3_slaveAddr)), addrInScratchpad(io.s1_paddr)) val s1_scratchpad_hit = Mux(s1_slaveValid, lineInScratchpad(scratchpadLine(s1s3_slaveAddr)), addrInScratchpad(io.s1_paddr))
val s2_scratchpad_hit = RegEnable(s1_scratchpad_hit, s1_clk_en) val s2_scratchpad_hit = RegEnable(s1_scratchpad_hit, s1_clk_en)
io.errors.correctable.foreach { c => io.errors.correctable.foreach { c =>
c.valid := s2_valid && Mux(s2_scratchpad_hit, s2_data_decoded.correctable, s2_disparity) c.valid := ((s2_valid || s2_slaveValid) && (s2_scratchpad_hit && s2_data_decoded.correctable)) || (s2_valid && !s2_scratchpad_hit && s2_disparity)
c.bits := 0.U c.bits := Mux(s2_scratchpad_hit, scratchpadBase.get + s2_scratchpad_word_addr, 0.U)
} }
io.errors.uncorrectable.foreach { u => io.errors.uncorrectable.foreach { u =>
u.valid := s2_valid && s2_scratchpad_hit && s2_data_decoded.uncorrectable u.valid := (s2_valid || s2_slaveValid) && (s2_scratchpad_hit && s2_data_decoded.uncorrectable)
u.bits := scratchpadBase.get + s2_scratchpad_word_addr // the Mux is not necessary, but saves HW in BusErrorUnit because it matches c.bits above
u.bits := Mux(s2_scratchpad_hit, scratchpadBase.get + s2_scratchpad_word_addr, 0.U)
} }
tl_in.map { tl => tl_in.map { tl =>