From 95d00b13cc99ce7160412aa1dcb4d4f611babe1e Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 6 Nov 2017 12:39:17 -0800 Subject: [PATCH] Report ITIM slave port errors to BusErrorUnit --- src/main/scala/rocket/ICache.scala | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index 40c705d8..872ebc01 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -273,12 +273,13 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) val s1_scratchpad_hit = Mux(s1_slaveValid, lineInScratchpad(scratchpadLine(s1s3_slaveAddr)), addrInScratchpad(io.s1_paddr)) val s2_scratchpad_hit = RegEnable(s1_scratchpad_hit, s1_clk_en) io.errors.correctable.foreach { c => - c.valid := s2_valid && Mux(s2_scratchpad_hit, s2_data_decoded.correctable, s2_disparity) - c.bits := 0.U + c.valid := ((s2_valid || s2_slaveValid) && (s2_scratchpad_hit && s2_data_decoded.correctable)) || (s2_valid && !s2_scratchpad_hit && s2_disparity) + c.bits := Mux(s2_scratchpad_hit, scratchpadBase.get + s2_scratchpad_word_addr, 0.U) } io.errors.uncorrectable.foreach { u => - u.valid := s2_valid && s2_scratchpad_hit && s2_data_decoded.uncorrectable - u.bits := scratchpadBase.get + s2_scratchpad_word_addr + u.valid := (s2_valid || s2_slaveValid) && (s2_scratchpad_hit && s2_data_decoded.uncorrectable) + // the Mux is not necessary, but saves HW in BusErrorUnit because it matches c.bits above + u.bits := Mux(s2_scratchpad_hit, scratchpadBase.get + s2_scratchpad_word_addr, 0.U) } tl_in.map { tl =>