tilelink2 HintHandler: fill in correct sink in responses
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@ -615,8 +615,7 @@ class TLEdgeIn(
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d
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}
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// !!! buggy! deduce sink from address
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def HintAck(a: TLBundleA, sink: UInt = UInt(0)): TLBundleD = HintAck(address(a), sink, a.source, a.size)
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def HintAck(a: TLBundleA, fromSink: UInt): TLBundleD = HintAck(address(a), fromSink, a.source, a.size)
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def HintAck(fromAddress: UInt, fromSink: UInt, toSource: UInt, lgSize: UInt) = {
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val d = Wire(new TLBundleD(bundle))
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d.opcode := TLMessages.HintAck
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@ -28,13 +28,14 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
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require (!supportClients || bce)
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if (supportManagers) {
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val handleA = if (passthrough) !edgeOut.manager.supportsHint(edgeIn.address(in.a.bits), edgeIn.size(in.a.bits)) else Bool(true)
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val address = edgeIn.address(in.a.bits)
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val handleA = if (passthrough) !edgeOut.manager.supportsHint(address, edgeIn.size(in.a.bits)) else Bool(true)
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val bypassD = handleA && in.a.bits.opcode === TLMessages.Hint
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// Prioritize existing D traffic over HintAck
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in.d.valid := out.d.valid || (bypassD && in.a.valid)
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out.d.ready := in.d.ready
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in.d.bits := Mux(out.d.valid, out.d.bits, edgeIn.HintAck(in.a.bits))
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in.d.bits := Mux(out.d.valid, out.d.bits, edgeIn.HintAck(in.a.bits, edgeOut.manager.findId(address)))
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in.a.ready := Mux(bypassD, in.d.ready && !out.d.valid, out.a.ready)
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out.a.valid := in.a.valid && !bypassD
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@ -177,6 +177,7 @@ case class TLManagerPortParameters(managers: Seq[TLManagerParameters], beatBytes
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// Synthesizable lookup methods
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def find(address: UInt) = Vec(managers.map(_.address.map(_.contains(address)).reduce(_ || _)))
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def findById(id: UInt) = Vec(managers.map(_.sinkId.contains(id)))
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def findId(address: UInt) = Mux1H(find(address), managers.map(m => UInt(m.sinkId.start)))
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// !!! need a cheaper version of find, where we assume a valid address match exists
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