From 94761f714d627538774f9f40e51896b5b264a82c Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Mon, 12 Sep 2016 17:26:40 -0700 Subject: [PATCH] tilelink2 HintHandler: fill in correct sink in responses --- src/main/scala/uncore/tilelink2/Edges.scala | 3 +-- src/main/scala/uncore/tilelink2/HintHandler.scala | 5 +++-- src/main/scala/uncore/tilelink2/Parameters.scala | 7 ++++--- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/Edges.scala b/src/main/scala/uncore/tilelink2/Edges.scala index 7b37c7cb..ceab2ca5 100644 --- a/src/main/scala/uncore/tilelink2/Edges.scala +++ b/src/main/scala/uncore/tilelink2/Edges.scala @@ -615,8 +615,7 @@ class TLEdgeIn( d } - // !!! buggy! deduce sink from address - def HintAck(a: TLBundleA, sink: UInt = UInt(0)): TLBundleD = HintAck(address(a), sink, a.source, a.size) + def HintAck(a: TLBundleA, fromSink: UInt): TLBundleD = HintAck(address(a), fromSink, a.source, a.size) def HintAck(fromAddress: UInt, fromSink: UInt, toSource: UInt, lgSize: UInt) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck diff --git a/src/main/scala/uncore/tilelink2/HintHandler.scala b/src/main/scala/uncore/tilelink2/HintHandler.scala index 277297d5..d44fa5f9 100644 --- a/src/main/scala/uncore/tilelink2/HintHandler.scala +++ b/src/main/scala/uncore/tilelink2/HintHandler.scala @@ -28,13 +28,14 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f require (!supportClients || bce) if (supportManagers) { - val handleA = if (passthrough) !edgeOut.manager.supportsHint(edgeIn.address(in.a.bits), edgeIn.size(in.a.bits)) else Bool(true) + val address = edgeIn.address(in.a.bits) + val handleA = if (passthrough) !edgeOut.manager.supportsHint(address, edgeIn.size(in.a.bits)) else Bool(true) val bypassD = handleA && in.a.bits.opcode === TLMessages.Hint // Prioritize existing D traffic over HintAck in.d.valid := out.d.valid || (bypassD && in.a.valid) out.d.ready := in.d.ready - in.d.bits := Mux(out.d.valid, out.d.bits, edgeIn.HintAck(in.a.bits)) + in.d.bits := Mux(out.d.valid, out.d.bits, edgeIn.HintAck(in.a.bits, edgeOut.manager.findId(address))) in.a.ready := Mux(bypassD, in.d.ready && !out.d.valid, out.a.ready) out.a.valid := in.a.valid && !bypassD diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala index 9648a3b5..fb36c41d 100644 --- a/src/main/scala/uncore/tilelink2/Parameters.scala +++ b/src/main/scala/uncore/tilelink2/Parameters.scala @@ -177,13 +177,14 @@ case class TLManagerPortParameters(managers: Seq[TLManagerParameters], beatBytes // Synthesizable lookup methods def find(address: UInt) = Vec(managers.map(_.address.map(_.contains(address)).reduce(_ || _))) def findById(id: UInt) = Vec(managers.map(_.sinkId.contains(id))) + def findId(address: UInt) = Mux1H(find(address), managers.map(m => UInt(m.sinkId.start))) // !!! need a cheaper version of find, where we assume a valid address match exists // Does this Port manage this ID/address? def contains(address: UInt) = find(address).reduce(_ || _) def containsById(id: UInt) = findById(id).reduce(_ || _) - + private def safety_helper(member: TLManagerParameters => TransferSizes)(address: UInt, lgSize: UInt) = { val allSame = managers.map(member(_) == member(managers(0))).reduce(_ && _) if (allSame) member(managers(0)).containsLg(lgSize) else { @@ -255,11 +256,11 @@ case class TLClientPortParameters(clients: Seq[TLClientParameters]) { // These return Option[TLClientParameters] for your convenience def find(id: Int) = clients.find(_.sourceId.contains(id)) - + // Synthesizable lookup methods def find(id: UInt) = Vec(clients.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ || _) - + private def safety_helper(member: TLClientParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = clients.map(member(_) == member(clients(0))).reduce(_ && _) if (allSame) member(clients(0)).containsLg(lgSize) else {