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tilelink2 HintHandler: fill in correct sink in responses

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This commit is contained in:
Wesley W. Terpstra 2016-09-12 17:26:40 -07:00
parent ca5f98f138
commit 94761f714d
3 changed files with 8 additions and 7 deletions
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3
src/main/scala/uncore/tilelink2/Edges.scala
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@ -615,8 +615,7 @@ class TLEdgeIn(
d d
} }
// !!! buggy! deduce sink from address def HintAck(a: TLBundleA, fromSink: UInt): TLBundleD = HintAck(address(a), fromSink, a.source, a.size)
def HintAck(a: TLBundleA, sink: UInt = UInt(0)): TLBundleD = HintAck(address(a), sink, a.source, a.size)
def HintAck(fromAddress: UInt, fromSink: UInt, toSource: UInt, lgSize: UInt) = { def HintAck(fromAddress: UInt, fromSink: UInt, toSource: UInt, lgSize: UInt) = {
val d = Wire(new TLBundleD(bundle)) val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck d.opcode := TLMessages.HintAck

5
src/main/scala/uncore/tilelink2/HintHandler.scala
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@ -28,13 +28,14 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
require (!supportClients || bce) require (!supportClients || bce)
if (supportManagers) { if (supportManagers) {
val handleA = if (passthrough) !edgeOut.manager.supportsHint(edgeIn.address(in.a.bits), edgeIn.size(in.a.bits)) else Bool(true) val address = edgeIn.address(in.a.bits)
val handleA = if (passthrough) !edgeOut.manager.supportsHint(address, edgeIn.size(in.a.bits)) else Bool(true)
val bypassD = handleA && in.a.bits.opcode === TLMessages.Hint val bypassD = handleA && in.a.bits.opcode === TLMessages.Hint
// Prioritize existing D traffic over HintAck // Prioritize existing D traffic over HintAck
in.d.valid := out.d.valid || (bypassD && in.a.valid) in.d.valid := out.d.valid || (bypassD && in.a.valid)
out.d.ready := in.d.ready out.d.ready := in.d.ready
in.d.bits := Mux(out.d.valid, out.d.bits, edgeIn.HintAck(in.a.bits)) in.d.bits := Mux(out.d.valid, out.d.bits, edgeIn.HintAck(in.a.bits, edgeOut.manager.findId(address)))
in.a.ready := Mux(bypassD, in.d.ready && !out.d.valid, out.a.ready) in.a.ready := Mux(bypassD, in.d.ready && !out.d.valid, out.a.ready)
out.a.valid := in.a.valid && !bypassD out.a.valid := in.a.valid && !bypassD

1
src/main/scala/uncore/tilelink2/Parameters.scala
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@ -177,6 +177,7 @@ case class TLManagerPortParameters(managers: Seq[TLManagerParameters], beatBytes
// Synthesizable lookup methods // Synthesizable lookup methods
def find(address: UInt) = Vec(managers.map(_.address.map(_.contains(address)).reduce(_ || _))) def find(address: UInt) = Vec(managers.map(_.address.map(_.contains(address)).reduce(_ || _)))
def findById(id: UInt) = Vec(managers.map(_.sinkId.contains(id))) def findById(id: UInt) = Vec(managers.map(_.sinkId.contains(id)))
def findId(address: UInt) = Mux1H(find(address), managers.map(m => UInt(m.sinkId.start)))
// !!! need a cheaper version of find, where we assume a valid address match exists // !!! need a cheaper version of find, where we assume a valid address match exists