riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink2 HintHandler: fill in correct sink in responses

Browse Source
This commit is contained in:
Wesley W. Terpstra
2016-09-12 17:26:40 -07:00
parent ca5f98f138
commit 94761f714d
3 changed files with 8 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/main/scala/uncore/tilelink2/Edges.scala
View File

@ -615,8 +615,7 @@ class TLEdgeIn(
d
}
// !!! buggy! deduce sink from address
def HintAck(a: TLBundleA, sink: UInt = UInt(0)): TLBundleD = HintAck(address(a), sink, a.source, a.size)
def HintAck(a: TLBundleA, fromSink: UInt): TLBundleD = HintAck(address(a), fromSink, a.source, a.size)
def HintAck(fromAddress: UInt, fromSink: UInt, toSource: UInt, lgSize: UInt) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck