add vector exception infrastructure

rocket/src/main/scala/consts.scala

@@ -139,6 +139,10 @@ object Constants
   val PCR_FROMHOST = UFix(17, 5);
   val PCR_VECBANK  = UFix(18, 5);
 
+  // temporaries for vector, these will go away
+  val PCR_VEC_TMP1 = UFix(30, 5)
+  val PCR_VEC_TMP2 = UFix(31, 5)
+
   // definition of bits in PCR status reg
   val SR_ET   = 0;  // enable traps
   val SR_EF   = 1;  // enable floating point

rocket/src/main/scala/cpu.scala

@@ -156,6 +156,10 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
     ctrl.io.vec_iface.vackq_valid := vu.io.vec_ackq.valid
     vu.io.vec_ackq.ready := ctrl.io.vec_iface.vackq_ready
 
+    // exceptions
+    // dpath.io.vec_iface.eaddr
+    // dpath.io.vec_iface.exception
+
     // hooking up vector memory interface
     ctrl.io.ext_mem.req_val := vu.io.dmem_req.valid
     ctrl.io.ext_mem.req_cmd := vu.io.dmem_req.bits.cmd

rocket/src/main/scala/dpath.scala

@@ -402,6 +402,8 @@ class rocketDpath extends Component
     vec.io.vecbankcnt := pcr.io.vecbankcnt
     vec.io.wdata := wb_reg_vec_wdata
     vec.io.rs2 := wb_reg_rs2
+    vec.io.vec_eaddr := pcr.io.vec_eaddr
+    vec.io.vec_exception := pcr.io.vec_exception
 
     wb_wdata :=
       Mux(vec.io.wen, Cat(Bits(0,52), vec.io.appvl),

rocket/src/main/scala/dpath_util.scala

@@ -80,6 +80,8 @@ class ioDpathPCR extends Bundle()
   val irq_ipi   = Bool(OUTPUT);
   val vecbank   = Bits(8, OUTPUT)
   val vecbankcnt = UFix(4, OUTPUT)
+  val vec_eaddr  = Bits(VADDR_BITS, OUTPUT)
+  val vec_exception = Bool(OUTPUT)
 }
 
 class rocketDpathPCR extends Component
@@ -98,6 +100,8 @@ class rocketDpathPCR extends Component
   val reg_k1       = Reg() { Bits() };
   val reg_ptbr     = Reg() { UFix() };
   val reg_vecbank  = Reg(resetVal = Bits("b1111_1111", 8))
+  val reg_vec_eaddr = Reg() { Bits() }
+  val reg_vec_exception = Reg() { Bool() }
   
   val reg_error_mode  = Reg(resetVal = Bool(false));
   val reg_status_vm   = Reg(resetVal = Bool(false));
@@ -139,6 +143,9 @@ class rocketDpathPCR extends Component
     cnt = cnt + reg_vecbank(i)
   io.vecbankcnt := cnt(3,0)
 
+  io.vec_eaddr := reg_vec_eaddr
+  io.vec_exception := reg_vec_exception
+
   val badvaddr_sign = Mux(io.w.data(VADDR_BITS-1), ~io.w.data(63,VADDR_BITS) === UFix(0), io.w.data(63,VADDR_BITS) != UFix(0))
   when (io.badvaddr_wen) {
     reg_badvaddr     := Cat(badvaddr_sign, io.w.data(VADDR_BITS-1,0)).toUFix;
@@ -205,6 +212,8 @@ class rocketDpathPCR extends Component
     when (waddr === PCR_K1)       { reg_k1          := wdata; }
     when (waddr === PCR_PTBR)     { reg_ptbr        := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
     when (waddr === PCR_VECBANK)  { reg_vecbank     := wdata(7,0) }
+    when (waddr === PCR_VEC_TMP1) { reg_vec_eaddr    := wdata(VADDR_BITS,0) }
+    when (waddr === PCR_VEC_TMP2) { reg_vec_exception:= wdata(0) }
   }
 
   rdata := Bits(0, 64)

rocket/src/main/scala/dpath_vec.scala

@@ -11,6 +11,8 @@ class ioDpathVecInterface extends Bundle
   val vcmdq_bits = Bits(SZ_VCMD, OUTPUT)
   val vximm1q_bits = Bits(SZ_VIMM, OUTPUT)
   val vximm2q_bits = Bits(SZ_VSTRIDE, OUTPUT)
+  val eaddr = Bits(64, OUTPUT)
+  val exception = Bool(OUTPUT)
 }
 
 class ioDpathVec extends Bundle
@@ -25,6 +27,8 @@ class ioDpathVec extends Bundle
   val vecbankcnt = UFix(4, INPUT)
   val wdata = Bits(64, INPUT)
   val rs2 = Bits(64, INPUT)
+  val vec_eaddr = Bits(64, INPUT)
+  val vec_exception = Bool(INPUT)
   val wen = Bool(OUTPUT)
   val appvl = UFix(12, OUTPUT)
 }
@@ -125,6 +129,9 @@ class rocketDpathVec extends Component
 
   io.iface.vximm2q_bits := io.rs2
 
+  io.iface.eaddr := io.vec_eaddr
+  io.iface.exception := io.vec_exception
+
   io.ctrl.valid := io.valid
   io.ctrl.inst := io.inst
   io.ctrl.appvl0 := reg_appvl0