riscv/rocket-chip
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add vector exception infrastructure

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This commit is contained in:
Yunsup Lee
2012-02-25 16:37:56 -08:00
parent 3839e3a318
commit 946e0c6e4e
5 changed files with 26 additions and 0 deletions
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9
rocket/src/main/scala/dpath_util.scala
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@ -80,6 +80,8 @@ class ioDpathPCR extends Bundle()
val irq_ipi = Bool(OUTPUT);
val vecbank = Bits(8, OUTPUT)
val vecbankcnt = UFix(4, OUTPUT)
val vec_eaddr = Bits(VADDR_BITS, OUTPUT)
val vec_exception = Bool(OUTPUT)
}
class rocketDpathPCR extends Component
@ -98,6 +100,8 @@ class rocketDpathPCR extends Component
val reg_k1 = Reg() { Bits() };
val reg_ptbr = Reg() { UFix() };
val reg_vecbank = Reg(resetVal = Bits("b1111_1111", 8))
val reg_vec_eaddr = Reg() { Bits() }
val reg_vec_exception = Reg() { Bool() }
val reg_error_mode = Reg(resetVal = Bool(false));
val reg_status_vm = Reg(resetVal = Bool(false));
@ -139,6 +143,9 @@ class rocketDpathPCR extends Component
cnt = cnt + reg_vecbank(i)
io.vecbankcnt := cnt(3,0)
io.vec_eaddr := reg_vec_eaddr
io.vec_exception := reg_vec_exception
val badvaddr_sign = Mux(io.w.data(VADDR_BITS-1), ~io.w.data(63,VADDR_BITS) === UFix(0), io.w.data(63,VADDR_BITS) != UFix(0))
when (io.badvaddr_wen) {
reg_badvaddr := Cat(badvaddr_sign, io.w.data(VADDR_BITS-1,0)).toUFix;
@ -205,6 +212,8 @@ class rocketDpathPCR extends Component
when (waddr === PCR_K1) { reg_k1 := wdata; }
when (waddr === PCR_PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
when (waddr === PCR_VECBANK) { reg_vecbank := wdata(7,0) }
when (waddr === PCR_VEC_TMP1) { reg_vec_eaddr := wdata(VADDR_BITS,0) }
when (waddr === PCR_VEC_TMP2) { reg_vec_exception:= wdata(0) }
}
rdata := Bits(0, 64)