Remove legacy devices that use AMOALU
I'm going to change the AMOALU API, and so I'm removing dependent dead code.
This commit is contained in:
Andrew Waterman
parent
f8151ce786
commit
938b089543
@ -1,423 +0,0 @@
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// See LICENSE.SiFive for license details.
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package uncore.converters
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import Chisel._
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import junctions._
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import uncore.tilelink._
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import uncore.util._
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import uncore.constants._
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import config._
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import HastiConstants._
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/* We need to translate TileLink requests into operations we can actually execute on AHB.
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* The general plan of attack is:
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* get => one AHB=>TL read
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* put => [multiple AHB write fragments=>nill], one AHB write=>TL
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* getBlock => AHB burst reads =>TL
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* putBlock => AHB burst writes=>TL
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* getPrefetch => noop=>TL
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* putPrefetch => noop=>TL
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* putAtomic => one AHB=>TL read, one idle, one AHB atom_write=>nill, one idle
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*
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* This requires that we support a pipeline of optional AHB requests with optional TL responses
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*/
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class AHBRequestIO(implicit p: Parameters) extends HastiMasterIO
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with HasGrantType
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with HasClientTransactionId
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with HasTileLinkBeatId {
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val executeAHB = Bool()
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val respondTL = Bool()
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val latchAtom = Bool()
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val firstBurst = Bool()
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val finalBurst = Bool()
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val cmd = Bits(width = M_SZ) // atomic op
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}
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// AHB stage1: translate TileLink Acquires into AHBRequests
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class AHBTileLinkIn(supportAtomics: Boolean = false)(implicit val p: Parameters) extends Module
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with HasHastiParameters
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with HasTileLinkParameters {
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val io = new Bundle {
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val acquire = new DecoupledIO(new Acquire).flip // NOTE: acquire must be either a Queue or a Pipe
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val request = new DecoupledIO(new AHBRequestIO)
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}
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// Match the AHB burst with a TileLink {Put,Get}Block
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val burstSize = tlDataBeats match {
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case 1 => HBURST_SINGLE
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// case 2 not supported by AHB
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case 4 => HBURST_WRAP4
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case 8 => HBURST_WRAP8
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case 16 => HBURST_WRAP16
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case _ => throw new java.lang.AssertionError("TileLink beats unsupported by AHB")
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}
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// Bursts start at 0 and wrap-around back to 0
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val finalBurst = UInt(tlDataBeats-1, width = log2Up(tlDataBeats)).asUInt
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val firstBurst = UInt(0, width = log2Up(tlDataBeats))
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val next_wmask = Wire(UInt(width = tlDataBytes)) // calculated below
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// State variables for processing more complicated TileLink Acquires
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val s_atom_r :: s_atom_idle1 :: s_atom_w :: s_atom_idle2 :: Nil = Enum(UInt(), 4)
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val atom_state = Reg(init = s_atom_r) // never changes if !supportAtomics
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val done_wmask = Reg(init = UInt(0, width = tlDataBytes))
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val burst = Reg(init = firstBurst)
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// Grab some view of the TileLink acquire
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val acq_wmask = io.acquire.bits.wmask()
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val isReadBurst = io.acquire.bits.is(Acquire.getBlockType)
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val isWriteBurst = io.acquire.bits.is(Acquire.putBlockType)
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val isBurst = isWriteBurst || isReadBurst
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val isAtomic = io.acquire.bits.is(Acquire.putAtomicType) && Bool(supportAtomics)
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val isPut = io.acquire.bits.is(Acquire.putType)
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// Final states?
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val last_wmask = next_wmask === acq_wmask
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val last_atom = atom_state === s_atom_idle2
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val last_burst = burst === finalBurst
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// Block the incoming request until we've fully consumed it
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// NOTE: the outgoing grant.valid may happen while acquire.ready is still false;
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// for this reason it is essential to have a Queue or a Pipe infront of acquire
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io.acquire.ready := io.request.ready && MuxLookup(io.acquire.bits.a_type, Bool(true), Array(
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Acquire.getType -> Bool(true),
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Acquire.getBlockType -> last_burst, // hold it until the last beat is burst
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Acquire.putType -> last_wmask, // only accept the put if we can fully consume its wmask
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Acquire.putBlockType -> Bool(true),
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Acquire.putAtomicType -> last_atom, // atomic operation stages complete
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Acquire.getPrefetchType -> Bool(true),
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Acquire.putPrefetchType -> Bool(true)))
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// Advance the fragment state
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when (io.request.ready && io.acquire.valid && isPut) {
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when (last_wmask) { // if this was the last fragment, restart FSM
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done_wmask := UInt(0)
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} .otherwise {
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done_wmask := next_wmask
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}
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}
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// Advance the burst state
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// We assume here that TileLink gives us all putBlock beats with nothing between them
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when (io.request.ready && io.acquire.valid && isBurst) {
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when (last_burst) {
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burst := UInt(0)
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} .otherwise {
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burst := burst + UInt(1)
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}
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}
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// Advance the atomic state machine
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when (io.request.ready && io.acquire.valid && isAtomic) {
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switch (atom_state) {
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is (s_atom_r) { atom_state := s_atom_idle1 }
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is (s_atom_idle1) { atom_state := s_atom_w } // idle1 => AMOALU runs on a different clock than AHB slave read
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is (s_atom_w) { atom_state := s_atom_idle2 }
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is (s_atom_idle2) { atom_state := s_atom_r } // idle2 state is required by AHB after hmastlock is lowered
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}
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}
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// Returns (range=0, range=-1, aligned_wmask, size)
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def mask_helper(in_0 : Bool, range : UInt): (Bool, Bool, UInt, UInt) = {
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val len = range.getWidth
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if (len == 1) {
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(range === UInt(0), range === UInt(1), in_0.asUInt() & range, UInt(0))
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} else {
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val mid = len / 2
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val lo = range(mid-1, 0)
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val hi = range(len-1, mid)
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val (lo_0, lo_1, lo_m, lo_s) = mask_helper(in_0, lo)
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val (hi_0, hi_1, hi_m, hi_s) = mask_helper(in_0 && lo_0, hi)
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val out_0 = lo_0 && hi_0
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val out_1 = lo_1 && hi_1
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val out_m = Cat(hi_m, lo_m) | Fill(len, (in_0 && out_1).asUInt())
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val out_s = Mux(out_1, UInt(log2Up(len)), Mux(lo_0, hi_s, lo_s))
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(out_0, out_1, out_m, out_s)
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}
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}
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val pending_wmask = acq_wmask & ~done_wmask
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val put_addr = PriorityEncoder(pending_wmask)
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val (wmask_0, _, exec_wmask, put_size) = mask_helper(Bool(true), pending_wmask)
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next_wmask := done_wmask | exec_wmask
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// Calculate the address, with consideration to put fragments and bursts
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val addr_block = io.acquire.bits.addr_block
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val addr_beatin= io.acquire.bits.addr_beat
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val addr_burst = Mux(isReadBurst, addr_beatin + burst, addr_beatin)
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val addr_byte = Mux(isPut, put_addr, io.acquire.bits.addr_byte())
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val addr_beat = Mux(isWriteBurst, UInt(0), addr_burst)
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val ahbAddr = Cat(addr_block, addr_burst, addr_byte)
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val ahbSize = Mux(isPut, put_size, Mux(isBurst, UInt(log2Ceil(tlDataBytes)), io.acquire.bits.op_size()))
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val ahbBurst = MuxLookup(io.acquire.bits.a_type, HBURST_SINGLE, Array(
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Acquire.getType -> HBURST_SINGLE,
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Acquire.getBlockType -> burstSize,
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Acquire.putType -> HBURST_SINGLE,
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Acquire.putBlockType -> burstSize,
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Acquire.putAtomicType -> HBURST_SINGLE,
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Acquire.getPrefetchType -> HBURST_SINGLE,
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Acquire.putPrefetchType -> HBURST_SINGLE))
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val ahbWrite = MuxLookup(io.acquire.bits.a_type, Bool(false), Array(
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Acquire.getType -> Bool(false),
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Acquire.getBlockType -> Bool(false),
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Acquire.putType -> Bool(true),
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Acquire.putBlockType -> Bool(true),
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Acquire.putAtomicType -> MuxLookup(atom_state, Bool(false), Array(
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s_atom_r -> Bool(false),
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s_atom_idle1 -> Bool(false), // don't care
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s_atom_w -> Bool(true),
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s_atom_idle2 -> Bool(true))), // don't care
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Acquire.getPrefetchType -> Bool(false), // don't care
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Acquire.putPrefetchType -> Bool(true))) // don't care
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val ahbExecute = MuxLookup(io.acquire.bits.a_type, Bool(false), Array(
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Acquire.getType -> Bool(true),
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Acquire.getBlockType -> Bool(true),
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Acquire.putType -> !wmask_0, // handle the case of a Put with no bytes!
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Acquire.putBlockType -> Bool(true),
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Acquire.putAtomicType -> MuxLookup(atom_state, Bool(false), Array(
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s_atom_r -> Bool(true),
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s_atom_idle1 -> Bool(false),
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s_atom_w -> Bool(true),
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s_atom_idle2 -> Bool(false))),
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Acquire.getPrefetchType -> Bool(false),
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Acquire.putPrefetchType -> Bool(false)))
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val respondTL = MuxLookup(io.acquire.bits.a_type, Bool(false), Array(
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Acquire.getType -> Bool(true),
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Acquire.getBlockType -> Bool(true),
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Acquire.putType -> last_wmask,
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Acquire.putBlockType -> last_burst,
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Acquire.putAtomicType -> MuxLookup(atom_state, Bool(false), Array(
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s_atom_r -> Bool(true), // they want the old data
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s_atom_idle1 -> Bool(false),
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s_atom_w -> Bool(false),
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s_atom_idle2 -> Bool(false))),
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Acquire.getPrefetchType -> Bool(true),
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Acquire.putPrefetchType -> Bool(true)))
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io.request.valid := io.acquire.valid
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io.request.bits.htrans := HTRANS_IDLE // unused/ignored
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io.request.bits.haddr := ahbAddr
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io.request.bits.hmastlock := isAtomic && atom_state =/= s_atom_idle2
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io.request.bits.hwrite := ahbWrite
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io.request.bits.hburst := ahbBurst
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io.request.bits.hsize := ahbSize
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io.request.bits.hprot := HPROT_DATA | HPROT_PRIVILEGED
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io.request.bits.hwdata := io.acquire.bits.data
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io.request.bits.executeAHB := ahbExecute
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io.request.bits.respondTL := respondTL
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io.request.bits.latchAtom := isAtomic && atom_state === s_atom_r
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io.request.bits.firstBurst := burst === firstBurst
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io.request.bits.finalBurst := burst === finalBurst || !isBurst
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io.request.bits.cmd := io.acquire.bits.op_code()
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io.request.bits.is_builtin_type := Bool(true)
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io.request.bits.g_type := io.acquire.bits.getBuiltInGrantType()
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io.request.bits.client_xact_id := io.acquire.bits.client_xact_id
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io.request.bits.addr_beat := addr_beat
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val debugBurst = Reg(UInt())
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when (io.request.valid) {
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debugBurst := addr_burst - burst
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}
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// We only support built-in TileLink requests
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assert(!io.acquire.valid || io.acquire.bits.is_builtin_type, "AHB bridge only supports builtin TileLink types")
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// Ensure alignment of address to size
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assert(!io.acquire.valid || (ahbAddr & ((UInt(1) << ahbSize) - UInt(1))) === UInt(0), "TileLink operation misaligned")
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// If this is a putBlock, make sure it moves properly
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assert(!io.acquire.valid || !isBurst || burst === firstBurst || debugBurst === addr_burst - burst, "TileLink putBlock beats not sequential")
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// We better not get an incomplete TileLink acquire
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assert(!io.acquire.valid || isBurst || burst === firstBurst, "TileLink never completed a putBlock")
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// If we disabled atomic support, we better not see a request
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assert(!io.acquire.bits.is(Acquire.putAtomicType) || Bool(supportAtomics))
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}
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// AHB stage2: execute AHBRequests
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class AHBBusMaster(supportAtomics: Boolean = false)(implicit val p: Parameters) extends Module
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with HasHastiParameters
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with HasTileLinkParameters {
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val io = new Bundle {
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val request = new DecoupledIO(new AHBRequestIO).flip
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val grant = new DecoupledIO(new Grant)
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val ahb = new HastiMasterIO()
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}
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// All AHB outputs are registered (they might be IOs)
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val midBurst = Reg(init = Bool(false))
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val htrans = Reg(init = HTRANS_IDLE)
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val haddr = Reg(UInt())
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val hmastlock = Reg(init = Bool(false))
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val hwrite = Reg(Bool())
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val hburst = Reg(UInt())
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val hsize = Reg(init = UInt(0, width = SZ_HSIZE))
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val hprot = Reg(UInt())
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val hwdata0 = Reg(Bits())
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val hwdata1 = Reg(Bits())
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val hrdata = Reg(Bits())
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io.ahb.htrans := htrans
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io.ahb.haddr := haddr
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io.ahb.hmastlock := hmastlock
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io.ahb.hwrite := hwrite
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io.ahb.hburst := hburst
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io.ahb.hsize := hsize
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io.ahb.hprot := hprot
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io.ahb.hwdata := hwdata1 // one cycle after the address phase
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// TileLink response data needed in data phase
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val respondTL0 = Reg(init = Bool(false))
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val respondTL1 = Reg(init = Bool(false))
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val latchAtom0 = Reg(init = Bool(false))
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val latchAtom1 = Reg(init = Bool(false))
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val executeAHB0 = Reg(init = Bool(false))
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val executeAHB1 = Reg(init = Bool(false))
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val bubble = Reg(init = Bool(true)) // nothing useful in address phase
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val cmd = Reg(Bits())
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val g_type0 = Reg(UInt())
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val g_type1 = Reg(UInt())
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val client_xact_id0 = Reg(Bits())
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val client_xact_id1 = Reg(Bits())
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val addr_beat0 = Reg(UInt())
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val addr_beat1 = Reg(UInt())
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val grant1 = Reg(new Grant)
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// It is allowed to progress from Idle/Busy during a wait state
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val addrReady = io.ahb.hready || bubble || (!executeAHB1 && !executeAHB0)
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val dataReady = io.ahb.hready || !executeAHB1
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// Only accept a new AHBRequest if we have enough buffer space in the pad
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// to accomodate a persistent drop in TileLink's grant.ready
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io.request.ready := addrReady && io.grant.ready
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// htrans must be updated even if no request is valid
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when (addrReady) {
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when (io.request.fire() && io.request.bits.executeAHB) {
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midBurst := !io.request.bits.finalBurst
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when (io.request.bits.firstBurst) {
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htrans := HTRANS_NONSEQ
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} .otherwise {
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htrans := HTRANS_SEQ
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}
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} .otherwise {
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when (midBurst) {
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htrans := HTRANS_BUSY
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} .otherwise {
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htrans := HTRANS_IDLE
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}
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}
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}
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// Address phase, clear repondTL when we have nothing to do
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when (addrReady) {
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when (io.request.fire()) {
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respondTL0 := io.request.bits.respondTL
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latchAtom0 := io.request.bits.latchAtom
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executeAHB0:= io.request.bits.executeAHB
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bubble := Bool(false)
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} .otherwise {
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respondTL0 := Bool(false)
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latchAtom0 := Bool(false)
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executeAHB0:= Bool(false)
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bubble := Bool(true) // an atom-injected Idle is not a bubble!
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}
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}
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// Transfer bulk address phase
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when (io.request.fire()) {
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haddr := io.request.bits.haddr
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hmastlock := io.request.bits.hmastlock
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hwrite := io.request.bits.hwrite
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hburst := io.request.bits.hburst
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hsize := io.request.bits.hsize
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hprot := io.request.bits.hprot
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hwdata0 := io.request.bits.hwdata
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cmd := io.request.bits.cmd
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g_type0 := io.request.bits.g_type
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client_xact_id0 := io.request.bits.client_xact_id
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addr_beat0 := io.request.bits.addr_beat
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}
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// Execute Atomic ops; unused and optimized away if !supportAtomics
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val amo_p = p.alterPartial({
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case CacheBlockOffsetBits => hastiAddrBits
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})
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val alu = Module(new AMOALU(hastiDataBits, rhsIsAligned = true)(amo_p))
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alu.io.addr := haddr
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alu.io.cmd := cmd
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alu.io.typ := hsize
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alu.io.rhs := hwdata0
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alu.io.lhs := hrdata
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// Transfer bulk data phase
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when (dataReady) {
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when (addrReady) {
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respondTL1 := respondTL0
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latchAtom1 := latchAtom0
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executeAHB1 := executeAHB0
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} .otherwise {
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respondTL1 := Bool(false)
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latchAtom1 := Bool(false)
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executeAHB1 := Bool(false)
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}
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hwdata1 := Mux(Bool(supportAtomics), alu.io.out, hwdata0)
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g_type1 := g_type0
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client_xact_id1 := client_xact_id0
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addr_beat1 := addr_beat0
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}
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// Latch the read result for an atomic operation
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when (dataReady && latchAtom1) {
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hrdata := io.ahb.hrdata
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}
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// Only issue TL grant when the slave has provided data
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io.grant.valid := dataReady && respondTL1
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io.grant.bits := Grant(
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is_builtin_type = Bool(true),
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g_type = g_type1,
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client_xact_id = client_xact_id1,
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manager_xact_id = UInt(0),
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addr_beat = addr_beat1,
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data = io.ahb.hrdata)
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// We cannot support errors from AHB to TileLink
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assert(!io.ahb.hresp, "AHB hresp error detected and cannot be reported via TileLink")
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}
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class AHBBridge(supportAtomics: Boolean = true)(implicit val p: Parameters) extends Module
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with HasHastiParameters
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with HasTileLinkParameters {
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val io = new Bundle {
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val tl = new ClientUncachedTileLinkIO().flip
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val ahb = new HastiMasterIO()
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}
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|
||||
// Hasti and TileLink widths must agree at this point in the topology
|
||||
require (tlDataBits == hastiDataBits)
|
||||
require (p(rocket.PAddrBits) == hastiAddrBits)
|
||||
|
||||
// AHB does not permit bursts to cross a 1KB boundary
|
||||
require (tlDataBits * tlDataBeats <= 1024*8)
|
||||
// tlDataBytes must be a power of 2
|
||||
require (1 << log2Ceil(tlDataBytes) == tlDataBytes)
|
||||
|
||||
// Create the sub-blocks
|
||||
val fsm = Module(new AHBTileLinkIn(supportAtomics))
|
||||
val bus = Module(new AHBBusMaster(supportAtomics))
|
||||
val pad = Module(new Queue(new Grant, 4))
|
||||
|
||||
fsm.io.acquire <> Queue(io.tl.acquire, 2) // Pipe is also acceptable
|
||||
bus.io.request <> fsm.io.request
|
||||
io.ahb <> bus.io.ahb
|
||||
io.tl.grant <> pad.io.deq
|
||||
|
||||
// The pad is needed to absorb AHB progress while !grant.ready
|
||||
// We are only 'ready' if the pad has at least 3 cycles of space
|
||||
bus.io.grant.ready := pad.io.count <= UInt(1)
|
||||
pad.io.enq.bits := bus.io.grant.bits
|
||||
pad.io.enq.valid := bus.io.grant.valid
|
||||
}
|
||||
@ -9,7 +9,6 @@ import rocket.PAddrBits
|
||||
import uncore.tilelink._
|
||||
import uncore.util._
|
||||
import uncore.constants._
|
||||
import uncore.devices.TileLinkTestRAM
|
||||
import unittest.UnitTest
|
||||
import config._
|
||||
|
||||
@ -604,183 +603,3 @@ class TileLinkIONarrower(innerTLId: String, outerTLId: String)
|
||||
sending_get := Bool(false)
|
||||
}
|
||||
}
|
||||
|
||||
class TileLinkWidthAdapterTest(implicit p: Parameters) extends UnitTest {
|
||||
val narrowConfig = p(TLKey(p(TLId)))
|
||||
val wideConfig = narrowConfig.copy(
|
||||
dataBeats = narrowConfig.dataBeats / 2)
|
||||
val adapterParams = p.alterPartial({ case TLKey("WIDE") => wideConfig })
|
||||
|
||||
val depth = 2 * narrowConfig.dataBeats
|
||||
val ram = Module(new TileLinkTestRAM(depth))
|
||||
val driver = Module(new DriverSet(
|
||||
(driverParams: Parameters) => {
|
||||
implicit val p = driverParams
|
||||
Seq(
|
||||
Module(new PutSweepDriver(depth)),
|
||||
Module(new PutMaskDriver),
|
||||
Module(new PutAtomicDriver),
|
||||
Module(new PutBlockSweepDriver(depth / narrowConfig.dataBeats)),
|
||||
Module(new PrefetchDriver),
|
||||
Module(new GetMultiWidthDriver))
|
||||
}))
|
||||
val widener = Module(new TileLinkIOWidener(p(TLId), "WIDE")(adapterParams))
|
||||
val narrower = Module(new TileLinkIONarrower("WIDE", p(TLId))(adapterParams))
|
||||
|
||||
widener.io.in <> driver.io.mem
|
||||
narrower.io.in <> widener.io.out
|
||||
ram.io <> narrower.io.out
|
||||
driver.io.start := io.start
|
||||
io.finished := driver.io.finished
|
||||
}
|
||||
|
||||
class TileLinkFragmenterSource(implicit p: Parameters) extends TLModule()(p) {
|
||||
val io = new Bundle {
|
||||
val in = Decoupled(new Acquire).flip
|
||||
val out = Decoupled(new Acquire)
|
||||
val que = Decoupled(UInt(width = tlBeatAddrBits))
|
||||
}
|
||||
|
||||
// Pipeline stage with acquire data; needed to ensure in.bits stay fixed when !in.ready
|
||||
val acq_valid = RegInit(Bool(false))
|
||||
val acq_bits = Reg(new Acquire)
|
||||
// The last beat of generate acquire to send
|
||||
val acq_last_beat = Reg(UInt(width = tlBeatAddrBits))
|
||||
val acq_last = acq_bits.addr_beat === acq_last_beat
|
||||
|
||||
// 'in' has the first beat?
|
||||
val in_multi_put = io.in.bits.isBuiltInType(Acquire.putBlockType)
|
||||
val in_multi_get = io.in.bits.isBuiltInType(Acquire.getBlockType)
|
||||
val in_first_beat = !in_multi_put || io.in.bits.addr_beat === UInt(0)
|
||||
|
||||
// Move stuff from acq to out whenever out is ready
|
||||
io.out.valid := acq_valid
|
||||
// When can acq accept a request?
|
||||
val acq_ready = !acq_valid || (acq_last && io.out.ready)
|
||||
// Move the first beat from in to acq only when both acq and que are ready
|
||||
io.in.ready := (!in_first_beat || io.que.ready) && acq_ready
|
||||
io.que.valid := (in_first_beat && io.in.valid) && acq_ready
|
||||
|
||||
// in.fire moves data from in to acq and (optionally) que
|
||||
// out.fire moves data from acq to out
|
||||
|
||||
// Desired flow control results:
|
||||
assert (!io.que.fire() || io.in.fire()) // 1. que.fire => in.fire
|
||||
assert (!(io.in.fire() && in_first_beat) || io.que.fire()) // 2. in.fire && in_first_beat => que.fire
|
||||
assert (!io.out.fire() || acq_valid) // 3. out.fire => acq_valid
|
||||
assert (!io.in.fire() || (!acq_valid || (io.out.fire() && acq_last))) // 4. in.fire => !acq_valid || (out.fire && acq_last)
|
||||
// Proofs:
|
||||
// 1. que.fire => que.ready && in.valid && acq_ready => in.ready && in.valid
|
||||
// 2. in.fire && in_first_beat => in.valid && acq_ready && [(!in_first_beat || que.ready) && in_first_beat] =>
|
||||
// in.valid && acq_ready && que.ready && in_first_beat => que.valid && que.ready
|
||||
// 3. out.fire => out.valid => acq_valid
|
||||
// 4. in.fire => acq_ready => !acq_valid || (acq_last && out.ready) =>
|
||||
// !acq_valid || (acq_valid && acq_last && out.ready) => !acq_valid || (acq_last && out.fire)
|
||||
|
||||
val multi_size = SInt(-1, width = tlBeatAddrBits).asUInt // TL2: use in.bits.size()/beatBits-1
|
||||
val in_sizeMinus1 = Mux(in_multi_get || in_multi_put, multi_size, UInt(0))
|
||||
val in_insertSizeMinus1 = Mux(in_multi_get, multi_size, UInt(0))
|
||||
|
||||
when (io.in.fire()) {
|
||||
// Theorem 4 makes this safe; we overwrite garbage, or replace the final acq
|
||||
acq_valid := Bool(true)
|
||||
acq_bits := io.in.bits
|
||||
acq_last_beat := io.in.bits.addr_beat + in_insertSizeMinus1
|
||||
// Replace this with size truncation in TL2:
|
||||
acq_bits.a_type := Mux(in_multi_put, Acquire.putType, Mux(in_multi_get, Acquire.getType, io.in.bits.a_type))
|
||||
} .elsewhen (io.out.fire()) {
|
||||
acq_valid := !acq_last // false => !in.valid || (!que.ready && in_first_beat)
|
||||
acq_bits.addr_beat := acq_bits.addr_beat + UInt(1)
|
||||
// acq_last && out.fire => acq_last && out.ready && acq_valid => acq_ready
|
||||
// Suppose in.valid, then !in.fire => !in.ready => !(!in_first_beat || que.ready) => !que.ready && in_first_beat
|
||||
}
|
||||
|
||||
// Safe by theorem 3
|
||||
io.out.bits := acq_bits
|
||||
// Safe by theorem 1
|
||||
io.que.bits := in_sizeMinus1
|
||||
}
|
||||
|
||||
class TileLinkFragmenterSink(implicit p: Parameters) extends TLModule()(p) {
|
||||
val io = new Bundle {
|
||||
val in = Decoupled(new Grant).flip
|
||||
val out = Decoupled(new Grant)
|
||||
val que = Decoupled(UInt(width = tlBeatAddrBits)).flip
|
||||
}
|
||||
|
||||
val count_valid = RegInit(Bool(false))
|
||||
val multi_op = Reg(Bool())
|
||||
val count_bits = Reg(UInt(width = tlBeatAddrBits))
|
||||
val last = count_bits === UInt(0)
|
||||
|
||||
val in_put = io.in.bits.isBuiltInType(Grant.putAckType)
|
||||
val in_get = io.in.bits.isBuiltInType(Grant.getDataBeatType)
|
||||
val deliver = last || in_get
|
||||
|
||||
// Accept the input, discarding the non-final put grant
|
||||
io.in.ready := count_valid && (io.out.ready || !deliver)
|
||||
// Output the grant whenever we want delivery
|
||||
io.out.valid := count_valid && io.in.valid && deliver
|
||||
// Take a new number whenever we deliver the last beat
|
||||
io.que.ready := !count_valid || (io.in.valid && io.out.ready && last)
|
||||
|
||||
// Desired flow control results:
|
||||
assert (!io.out.fire() || (count_valid && io.in.fire())) // 1. out.fire => in.fire && count_valid
|
||||
assert (!(io.in.fire() && deliver) || io.out.fire()) // 2. in.fire && deliver => out.fire
|
||||
assert (!(io.out.fire() && last) || io.que.ready) // 3. out.fire && last => que.ready
|
||||
assert (!io.que.fire() || (!count_valid || io.out.fire())) // 4. que.fire => !count_valid || (out.fire && last)
|
||||
// Proofs:
|
||||
// 1. out.fire => out.ready && (count_valid && in.valid && deliver) => (count_valid && out.ready) && in.valid => in.fire
|
||||
// 2. in.fire && deliver => in.valid && count_valid && [(out.ready || !deliver) && deliver] =>
|
||||
// in.valid && count_valid && deliver && out.ready => out.fire
|
||||
// 3. out.fire && last => out.valid && out.ready && last => in.valid && out.ready && last => que.ready
|
||||
// 4. que.fire => que.valid && (!count_valid || (in.valid && out.ready && last))
|
||||
// => !count_valid || (count_valid && in.valid && out.ready && [last => deliver])
|
||||
// => !count_valid || (out.valid && out.ready && last)
|
||||
|
||||
when (io.que.fire()) {
|
||||
// Theorem 4 makes this safe; we overwrite garbage or last output
|
||||
count_valid := Bool(true)
|
||||
count_bits := io.que.bits
|
||||
multi_op := io.que.bits =/= UInt(0)
|
||||
} .elsewhen (io.in.fire()) {
|
||||
count_valid := !last // false => !que.valid
|
||||
count_bits := count_bits - UInt(1)
|
||||
// Proof: in.fire && [last => deliver] =2=> out.fire && last =3=> que.ready
|
||||
// !que.fire && que.ready => !que.valid
|
||||
}
|
||||
|
||||
// Safe by Theorem 1
|
||||
io.out.bits := io.in.bits
|
||||
io.out.bits.g_type := Mux(multi_op, Mux(in_get, Grant.getDataBlockType, Grant.putAckType), io.in.bits.g_type)
|
||||
}
|
||||
|
||||
class TileLinkFragmenter(depth: Int = 1)(implicit p: Parameters) extends TLModule()(p) {
|
||||
val io = new Bundle {
|
||||
val in = new ClientUncachedTileLinkIO().flip
|
||||
val out = new ClientUncachedTileLinkIO
|
||||
}
|
||||
|
||||
// TL2:
|
||||
// supportsAcquire = false
|
||||
// modify all outward managers to supportsMultibeat = true
|
||||
// assert: all managers must behaveFIFO (not inspect duplicated id field)
|
||||
|
||||
val source = Module(new TileLinkFragmenterSource)
|
||||
val sink = Module(new TileLinkFragmenterSink)
|
||||
sink.io.que <> Queue(source.io.que, depth)
|
||||
|
||||
source.io.in <> io.in.acquire
|
||||
io.out.acquire <> source.io.out
|
||||
sink.io.in <> io.out.grant
|
||||
io.in.grant <> sink.io.out
|
||||
}
|
||||
|
||||
object TileLinkFragmenter {
|
||||
// Pass the source/client to fragment
|
||||
def apply(source: ClientUncachedTileLinkIO, depth: Int = 1): ClientUncachedTileLinkIO = {
|
||||
val fragmenter = Module(new TileLinkFragmenter(depth)(source.p))
|
||||
fragmenter.io.in <> source
|
||||
fragmenter.io.out
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,187 +0,0 @@
|
||||
// See LICENSE.SiFive for license details.
|
||||
// See LICENSE.Berkeley for license details.
|
||||
|
||||
package uncore.devices
|
||||
|
||||
import Chisel._
|
||||
import config._
|
||||
import unittest.UnitTest
|
||||
import junctions._
|
||||
import uncore.tilelink._
|
||||
import uncore.util._
|
||||
import util._
|
||||
import HastiConstants._
|
||||
|
||||
class BRAMSlave(depth: Int)(implicit val p: Parameters) extends Module
|
||||
with HasTileLinkParameters {
|
||||
val io = new ClientUncachedTileLinkIO().flip
|
||||
|
||||
// For TL2:
|
||||
// supportsAcquire = false
|
||||
// supportsMultibeat = false
|
||||
// supportsHint = false
|
||||
// supportsAtomic = false
|
||||
|
||||
// Timing-wise, we assume the input is coming out of registers
|
||||
// since you probably needed a TileLinkFragmenter infront of us
|
||||
|
||||
// Thus, only one pipeline stage: the grant result
|
||||
val g_valid = RegInit(Bool(false))
|
||||
val g_bits = Reg(new Grant)
|
||||
|
||||
// Just pass the pipeline straight through
|
||||
io.grant.valid := g_valid
|
||||
io.grant.bits := g_bits
|
||||
io.acquire.ready := !g_valid || io.grant.ready
|
||||
|
||||
val acq_get = io.acquire.bits.isBuiltInType(Acquire.getType)
|
||||
val acq_put = io.acquire.bits.isBuiltInType(Acquire.putType)
|
||||
val acq_addr = Cat(io.acquire.bits.addr_block, io.acquire.bits.addr_beat)
|
||||
|
||||
val bram = Mem(depth, Bits(width = tlDataBits))
|
||||
|
||||
val ren = acq_get && io.acquire.fire()
|
||||
val wen = acq_put && io.acquire.fire()
|
||||
|
||||
when (io.grant.fire()) {
|
||||
g_valid := Bool(false)
|
||||
}
|
||||
|
||||
when (io.acquire.fire()) {
|
||||
g_valid := Bool(true)
|
||||
g_bits := Grant(
|
||||
is_builtin_type = Bool(true),
|
||||
g_type = io.acquire.bits.getBuiltInGrantType(),
|
||||
client_xact_id = io.acquire.bits.client_xact_id,
|
||||
manager_xact_id = UInt(0),
|
||||
addr_beat = io.acquire.bits.addr_beat,
|
||||
data = UInt(0))
|
||||
}
|
||||
|
||||
when (wen) {
|
||||
bram.write(acq_addr, io.acquire.bits.data)
|
||||
assert(io.acquire.bits.wmask().andR, "BRAMSlave: partial write masks not supported")
|
||||
}
|
||||
io.grant.bits.data := RegEnable(bram.read(acq_addr), ren)
|
||||
}
|
||||
|
||||
class HastiRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p) {
|
||||
val io = new HastiSlaveIO
|
||||
|
||||
val wdata = Vec.tabulate(hastiDataBytes)(i => io.hwdata(8*(i+1)-1,8*i))
|
||||
val waddr = Reg(UInt(width = hastiAddrBits))
|
||||
val wvalid = Reg(init = Bool(false))
|
||||
val wsize = Reg(UInt(width = SZ_HSIZE))
|
||||
val ram = SeqMem(depth, Vec(hastiDataBytes, Bits(width = 8)))
|
||||
|
||||
val max_size = log2Ceil(hastiDataBytes)
|
||||
val wmask_lut = MuxLookup(wsize, SInt(-1, hastiDataBytes).asUInt,
|
||||
(0 until max_size).map(sz => (UInt(sz) -> UInt((1 << (1 << sz)) - 1))))
|
||||
val wmask = (wmask_lut << waddr(max_size - 1, 0))(hastiDataBytes - 1, 0)
|
||||
|
||||
val is_trans = io.hsel && io.htrans.isOneOf(HTRANS_NONSEQ, HTRANS_SEQ)
|
||||
val raddr = io.haddr >> UInt(max_size)
|
||||
val ren = is_trans && !io.hwrite
|
||||
val bypass = Reg(init = Bool(false))
|
||||
|
||||
when (is_trans && io.hwrite) {
|
||||
waddr := io.haddr
|
||||
wsize := io.hsize
|
||||
wvalid := Bool(true)
|
||||
} .otherwise { wvalid := Bool(false) }
|
||||
|
||||
when (ren) { bypass := wvalid && (waddr >> UInt(max_size)) === raddr }
|
||||
|
||||
when (wvalid) {
|
||||
ram.write(waddr >> UInt(max_size), wdata, wmask.toBools)
|
||||
}
|
||||
|
||||
val rdata = ram.read(raddr, ren)
|
||||
io.hrdata := Cat(rdata.zip(wmask.toBools).zip(wdata).map {
|
||||
case ((rbyte, wsel), wbyte) => Mux(wsel && bypass, wbyte, rbyte)
|
||||
}.reverse)
|
||||
|
||||
io.hready := Bool(true)
|
||||
io.hresp := HRESP_OKAY
|
||||
}
|
||||
|
||||
/**
|
||||
* This RAM is not meant to be particularly performant.
|
||||
* It just supports the entire range of uncached TileLink operations in the
|
||||
* simplest way possible.
|
||||
*/
|
||||
class TileLinkTestRAM(depth: Int)(implicit val p: Parameters) extends Module
|
||||
with HasTileLinkParameters {
|
||||
val io = new ClientUncachedTileLinkIO().flip
|
||||
|
||||
val ram = Mem(depth, UInt(width = tlDataBits))
|
||||
|
||||
val responding = Reg(init = Bool(false))
|
||||
val acq = io.acquire.bits
|
||||
val r_acq = Reg(io.acquire.bits)
|
||||
val acq_addr = Cat(acq.addr_block, acq.addr_beat)
|
||||
val r_acq_addr = Cat(r_acq.addr_block, r_acq.addr_beat)
|
||||
|
||||
when (io.acquire.fire() && io.acquire.bits.last()) {
|
||||
r_acq := io.acquire.bits
|
||||
responding := Bool(true)
|
||||
}
|
||||
|
||||
when (io.grant.fire()) {
|
||||
val is_getblk = r_acq.isBuiltInType(Acquire.getBlockType)
|
||||
val last_beat = r_acq.addr_beat === UInt(tlDataBeats - 1)
|
||||
when (is_getblk && !last_beat) {
|
||||
r_acq.addr_beat := r_acq.addr_beat + UInt(1)
|
||||
} .otherwise { responding := Bool(false) }
|
||||
}
|
||||
|
||||
val old_data = ram(acq_addr)
|
||||
val new_data = acq.data
|
||||
val r_old_data = RegEnable(old_data, io.acquire.fire())
|
||||
|
||||
io.acquire.ready := !responding
|
||||
io.grant.valid := responding
|
||||
io.grant.bits := Grant(
|
||||
is_builtin_type = Bool(true),
|
||||
g_type = r_acq.getBuiltInGrantType(),
|
||||
client_xact_id = r_acq.client_xact_id,
|
||||
manager_xact_id = UInt(0),
|
||||
addr_beat = r_acq.addr_beat,
|
||||
data = Mux(r_acq.isAtomic(), r_old_data, ram(r_acq_addr)))
|
||||
|
||||
val amo_shift_bits = acq.amo_shift_bytes() << UInt(3)
|
||||
val amoalu = Module(new AMOALU(amoAluOperandBits, rhsIsAligned = true))
|
||||
amoalu.io.addr := Cat(acq.addr_block, acq.addr_beat, acq.addr_byte())
|
||||
amoalu.io.cmd := acq.op_code()
|
||||
amoalu.io.typ := acq.op_size()
|
||||
amoalu.io.lhs := old_data >> amo_shift_bits
|
||||
amoalu.io.rhs := new_data >> amo_shift_bits
|
||||
|
||||
val result = Mux(acq.isAtomic(), amoalu.io.out << amo_shift_bits, new_data)
|
||||
val wmask = FillInterleaved(8, acq.wmask())
|
||||
|
||||
when (io.acquire.fire() && acq.hasData()) {
|
||||
ram(acq_addr) := (old_data & ~wmask) | (result & wmask)
|
||||
}
|
||||
}
|
||||
|
||||
class TileLinkRAMTest(implicit val p: Parameters)
|
||||
extends UnitTest with HasTileLinkParameters {
|
||||
|
||||
val depth = 2 * tlDataBeats
|
||||
val ram = Module(new TileLinkTestRAM(depth))
|
||||
val driver = Module(new DriverSet(
|
||||
(driverParams: Parameters) => {
|
||||
implicit val p = driverParams
|
||||
Seq(
|
||||
Module(new PutSweepDriver(depth)),
|
||||
Module(new PutMaskDriver),
|
||||
Module(new PutAtomicDriver),
|
||||
Module(new PutBlockSweepDriver(depth / tlDataBeats)),
|
||||
Module(new PrefetchDriver),
|
||||
Module(new GetMultiWidthDriver))
|
||||
}))
|
||||
ram.io <> driver.io.mem
|
||||
driver.io.start := io.start
|
||||
io.finished := driver.io.finished
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user