Refactor L2 transaction trackers to each be capable of processing Voluntary Writebacks.
To elide several races between reading and writing the metadata array for different types of transactions, all L2XactTrackers can now sink Voluntary Releases (writebacks from the L1 in the current implementation). These writebacks are merged with the ongoing transaction, and the merging tracker supplies an acknowledgment of the writeback in addition to its ongoing activities. This change involved another refactoring of the control logic for allocating new trackers and routing incoming Acquires and Releases. BroadcastHub uses the new routing logic, but still processes all voluntary releases through the VoluntaryReleaseTracker (not a problem because there are no metadata update races). Closes #18 Closes #20
This commit is contained in:
Henry Cook
@ -52,26 +52,22 @@ class L2BroadcastHub(implicit p: Parameters) extends ManagerCoherenceAgent()(p)
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val sdq_val = Reg(init=Bits(0, sdqDepth))
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val sdq_alloc_id = PriorityEncoder(~sdq_val)
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val sdq_rdy = !sdq_val.andR
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val sdq_enq = io.inner.acquire.fire() && io.iacq().hasData()
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val sdq_enq = trackerList.map(_.io.alloc.iacq).reduce(_||_) &&
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io.inner.acquire.fire() &&
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io.iacq().hasData()
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when (sdq_enq) { sdq(sdq_alloc_id) := io.iacq().data }
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// Handle acquire transaction initiation
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val trackerAcquireIOs = trackerList.map(_.io.inner.acquire)
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val acquireConflicts = Vec(trackerList.map(_.io.has_acquire_conflict)).toBits
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val acquireMatches = Vec(trackerList.map(_.io.has_acquire_match)).toBits
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val acquireReadys = Vec(trackerAcquireIOs.map(_.ready)).toBits
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val acquire_idx = Mux(acquireMatches.orR,
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PriorityEncoder(acquireMatches),
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PriorityEncoder(acquireReadys))
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val block_acquires = acquireConflicts.orR || !sdq_rdy
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io.inner.acquire.ready := acquireReadys.orR && !block_acquires
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trackerAcquireIOs.zipWithIndex.foreach {
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case(tracker, i) =>
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tracker.bits := io.inner.acquire.bits
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tracker.bits.data := DataQueueLocation(sdq_alloc_id, inStoreQueue).toBits
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tracker.valid := io.inner.acquire.valid && !block_acquires && (acquire_idx === UInt(i))
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val sdqLoc = List.fill(nTransactors) {
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DataQueueLocation(sdq_alloc_id, inStoreQueue).toBits
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}
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doInputRoutingWithAllocation(
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io.inner.acquire,
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trackerList.map(_.io.inner.acquire),
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trackerList.map(_.io.matches.iacq),
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trackerList.map(_.io.alloc.iacq),
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Some(sdqLoc),
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Some(sdq_rdy))
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// Queue to store impending Voluntary Release data
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val voluntary = io.irel().isVoluntary()
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@ -81,17 +77,16 @@ class L2BroadcastHub(implicit p: Parameters) extends ManagerCoherenceAgent()(p)
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when(vwbdq_enq) { vwbdq(rel_data_cnt) := io.irel().data }
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// Handle releases, which might be voluntary and might have data
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val trackerReleaseIOs = trackerList.map(_.io.inner.release)
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val releaseReadys = Vec(trackerReleaseIOs.map(_.ready)).toBits
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io.inner.release.ready := releaseReadys.orR
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trackerReleaseIOs.zipWithIndex.foreach {
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case(tracker, i) =>
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tracker.valid := io.inner.release.valid
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tracker.bits := io.inner.release.bits
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tracker.bits.data := DataQueueLocation(rel_data_cnt,
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(if(i < nReleaseTransactors) inVolWBQueue
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else inClientReleaseQueue)).toBits
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}
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val vwbqLoc = (0 until nTransactors).map(i =>
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(DataQueueLocation(rel_data_cnt,
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(if(i < nReleaseTransactors) inVolWBQueue
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else inClientReleaseQueue)).toBits))
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doInputRoutingWithAllocation(
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io.inner.release,
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trackerList.map(_.io.inner.release),
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trackerList.map(_.io.matches.irel),
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trackerList.map(_.io.alloc.irel),
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Some(vwbqLoc))
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// Wire probe requests and grant reply to clients, finish acks from clients
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// Note that we bypass the Grant data subbundles
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@ -162,12 +157,12 @@ class BroadcastVoluntaryReleaseTracker(trackerId: Int)
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// Send an acknowledgement
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io.inner.grant.valid := state === s_busy && pending_ignt && !pending_irels && io.outer.grant.valid
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io.inner.grant.bits := coh.makeGrant(xact, UInt(trackerId))
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io.inner.grant.bits := coh.makeGrant(xact)
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when(io.inner.grant.fire()) { pending_ignt := Bool(false) }
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io.outer.grant.ready := state === s_busy && io.inner.grant.ready
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// State machine updates and transaction handler metadata intialization
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when(state === s_idle && io.inner.release.fire()) {
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when(state === s_idle && io.inner.release.valid && io.alloc.irel) {
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xact := io.irel()
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when(io.irel().hasMultibeatData()) {
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pending_irels := dropPendingBitWhenBeatHasData(io.inner.release)
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@ -181,8 +176,9 @@ class BroadcastVoluntaryReleaseTracker(trackerId: Int)
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when(state === s_busy && all_pending_done) { state := s_idle }
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// These IOs are used for routing in the parent
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io.has_acquire_match := Bool(false)
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io.has_acquire_conflict := Bool(false)
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io.matches.iacq := (state =/= s_idle) && xact.conflicts(io.iacq())
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io.matches.irel := (state =/= s_idle) && xact.conflicts(io.irel()) && io.irel().isVoluntary()
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io.matches.oprb := Bool(false)
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// Checks for illegal behavior
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assert(!(state === s_idle && io.inner.release.fire() && !io.irel().isVoluntary()),
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@ -221,11 +217,10 @@ class BroadcastAcquireTracker(trackerId: Int)
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val pending_outer_read_ = coh.makeGrant(io.iacq(), UInt(trackerId)).hasData()
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val subblock_type = xact.isSubBlockType()
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io.has_acquire_conflict := xact.conflicts(io.iacq()) &&
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(state =/= s_idle) &&
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!collect_iacq_data
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io.has_acquire_match := xact.conflicts(io.iacq()) &&
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collect_iacq_data
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// These IOs are used for routing in the parent
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io.matches.iacq := (state =/= s_idle) && xact.conflicts(io.iacq())
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io.matches.irel := (state =/= s_idle) && xact.conflicts(io.irel()) && !io.irel().isVoluntary()
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io.matches.oprb := Bool(false)
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val outerParams = p.alterPartial({ case TLId => outerTLId })
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@ -286,7 +281,7 @@ class BroadcastAcquireTracker(trackerId: Int)
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io.iacq().client_xact_id =/= xact.client_xact_id),
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"AcquireTracker accepted data beat from different client transaction than initial request.")
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assert(!(state === s_idle && io.inner.acquire.fire() &&
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assert(!(state === s_idle && io.inner.acquire.fire() && io.alloc.iacq &&
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io.iacq().hasMultibeatData() && io.iacq().addr_beat =/= UInt(0)),
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"AcquireTracker initialized with a tail data beat.")
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@ -309,7 +304,7 @@ class BroadcastAcquireTracker(trackerId: Int)
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switch (state) {
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is(s_idle) {
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io.inner.acquire.ready := Bool(true)
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when(io.inner.acquire.valid) {
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when(io.inner.acquire.valid && io.alloc.iacq) {
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xact := io.iacq()
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xact.data_buffer(UInt(0)) := io.iacq().data
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xact.wmask_buffer(UInt(0)) := io.iacq().wmask()
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@ -333,7 +328,7 @@ class BroadcastAcquireTracker(trackerId: Int)
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}
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// Handle releases, which may have data to be written back
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val matches = xact.conflicts(io.irel()) && !io.irel().isVoluntary()
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val matches = io.matches.irel
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io.inner.release.ready := (!io.irel().hasData() || io.outer.acquire.ready) && matches
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when(io.inner.release.valid && matches) {
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when(io.irel().hasData()) {
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