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tilelink2: make TLRational have configurable direction

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This commit is contained in:
Wesley W. Terpstra 2017-02-17 04:19:00 +01:00
parent bb334a2cf5
commit 924afebbd9
4 changed files with 44 additions and 32 deletions
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29
src/main/scala/uncore/tilelink2/Nodes.scala
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@ -7,6 +7,7 @@ import chisel3.internal.sourceinfo.SourceInfo
import config._ import config._
import diplomacy._ import diplomacy._
import scala.collection.mutable.ListBuffer import scala.collection.mutable.ListBuffer
import util.RationalDirection
case object TLMonitorBuilder extends Field[TLMonitorArgs => Option[TLMonitorBase]] case object TLMonitorBuilder extends Field[TLMonitorArgs => Option[TLMonitorBase]]
case object TLFuzzReadyValid extends Field[Boolean] case object TLFuzzReadyValid extends Field[Boolean]
@ -182,20 +183,20 @@ case class TLAsyncSinkNode(depth: Int, sync: Int)
dFn = { p => p.base.copy(minLatency = sync+1) }, dFn = { p => p.base.copy(minLatency = sync+1) },
uFn = { p => TLAsyncManagerPortParameters(depth, p) }) uFn = { p => TLAsyncManagerPortParameters(depth, p) })
object TLRationalImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeParameters, TLEdgeParameters, TLRationalBundle] object TLRationalImp extends NodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalEdgeParameters, TLRationalBundle]
{ {
def edgeO(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeParameters = TLEdgeParameters(pd, pu) def edgeO(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu)
def edgeI(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeParameters = TLEdgeParameters(pd, pu) def edgeI(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu)
def bundleO(eo: Seq[TLEdgeParameters]): Vec[TLRationalBundle] = Vec(eo.size, new TLRationalBundle(TLBundleParameters.union(eo.map(_.bundle)))) def bundleO(eo: Seq[TLRationalEdgeParameters]): Vec[TLRationalBundle] = Vec(eo.size, new TLRationalBundle(TLBundleParameters.union(eo.map(_.bundle))))
def bundleI(ei: Seq[TLEdgeParameters]): Vec[TLRationalBundle] = Vec(ei.size, new TLRationalBundle(TLBundleParameters.union(ei.map(_.bundle)))) def bundleI(ei: Seq[TLRationalEdgeParameters]): Vec[TLRationalBundle] = Vec(ei.size, new TLRationalBundle(TLBundleParameters.union(ei.map(_.bundle))))
def colour = "#00ff00" // green def colour = "#00ff00" // green
override def mixO(pd: TLClientPortParameters, node: OutwardNode[TLClientPortParameters, TLManagerPortParameters, TLRationalBundle]): TLClientPortParameters = override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(clients = pd.clients.map { c => c.copy (nodePath = node +: c.nodePath) }) pd.copy(base = pd.base.copy(clients = pd.base.clients.map { c => c.copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLManagerPortParameters, node: InwardNode[TLClientPortParameters, TLManagerPortParameters, TLRationalBundle]): TLManagerPortParameters = override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(managers = pu.managers.map { m => m.copy (nodePath = node +: m.nodePath) }) pu.copy(base = pu.base.copy(managers = pu.base.managers.map { m => m.copy (nodePath = node +: m.nodePath) }))
} }
case class TLRationalIdentityNode() extends IdentityNode(TLRationalImp) case class TLRationalIdentityNode() extends IdentityNode(TLRationalImp)
@ -204,10 +205,10 @@ case class TLRationalInputNode() extends InputNode(TLRationalImp)
case class TLRationalSourceNode() case class TLRationalSourceNode()
extends MixedAdapterNode(TLImp, TLRationalImp)( extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => p }, dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.copy(minLatency = 1) }) // discard cycles from other clock domain uFn = { p => p.base.copy(minLatency = 1) }) // discard cycles from other clock domain
case class TLRationalSinkNode() case class TLRationalSinkNode(direction: RationalDirection)
extends MixedAdapterNode(TLRationalImp, TLImp)( extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.copy(minLatency = 1) }, dFn = { p => p.base.copy(minLatency = 1) },
uFn = { p => p }) uFn = { p => TLRationalManagerPortParameters(direction, p) })

9
src/main/scala/uncore/tilelink2/Parameters.scala
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@ -5,6 +5,7 @@ package uncore.tilelink2
import Chisel._ import Chisel._
import diplomacy._ import diplomacy._
import scala.math.max import scala.math.max
import util.RationalDirection
case class TLManagerParameters( case class TLManagerParameters(
address: Seq[AddressSet], address: Seq[AddressSet],
@ -326,6 +327,14 @@ case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: T
val bundle = TLAsyncBundleParameters(manager.depth, TLBundleParameters(client.base, manager.base)) val bundle = TLAsyncBundleParameters(manager.depth, TLBundleParameters(client.base, manager.base))
} }
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLManagerPortParameters)
case class TLRationalClientPortParameters(base: TLClientPortParameters)
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters)
{
val bundle = TLBundleParameters(client.base, manager.base)
}
object ManagerUnification object ManagerUnification
{ {
def apply(managers: Seq[TLManagerParameters]) = { def apply(managers: Seq[TLManagerParameters]) = {

36
src/main/scala/uncore/tilelink2/RationalCrossing.scala
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@ -27,14 +27,15 @@ class TLRationalCrossingSource(implicit p: Parameters) extends LazyModule
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) => ((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe
val direction = edgeOut.manager.direction
out.a <> ToRational(in.a) out.a <> ToRational(in.a, direction)
in.d <> FromRational(out.d) in.d <> FromRational(out.d, direction.flip)
if (bce) { if (bce) {
in.b <> FromRational(out.b) in.b <> FromRational(out.b, direction.flip)
out.c <> ToRational(in.c) out.c <> ToRational(in.c, direction)
out.e <> ToRational(in.e) out.e <> ToRational(in.e, direction)
} else { } else {
in.b.valid := Bool(false) in.b.valid := Bool(false)
in.c.ready := Bool(true) in.c.ready := Bool(true)
@ -50,9 +51,9 @@ class TLRationalCrossingSource(implicit p: Parameters) extends LazyModule
} }
} }
class TLRationalCrossingSink(implicit p: Parameters) extends LazyModule class TLRationalCrossingSink(direction: RationalDirection = Symmetric)(implicit p: Parameters) extends LazyModule
{ {
val node = TLRationalSinkNode() val node = TLRationalSinkNode(direction)
lazy val module = new LazyModuleImp(this) { lazy val module = new LazyModuleImp(this) {
val io = new Bundle { val io = new Bundle {
@ -62,14 +63,15 @@ class TLRationalCrossingSink(implicit p: Parameters) extends LazyModule
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) => ((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
val bce = edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe val bce = edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe
val direction = edgeIn.manager.direction
out.a <> FromRational(in.a) out.a <> FromRational(in.a, direction)
in.d <> ToRational(out.d) in.d <> ToRational(out.d, direction.flip)
if (bce) { if (bce) {
in.b <> ToRational(out.b) in.b <> ToRational(out.b, direction.flip)
out.c <> FromRational(in.c) out.c <> FromRational(in.c, direction)
out.e <> FromRational(in.e) out.e <> FromRational(in.e, direction)
} else { } else {
out.b.ready := Bool(true) out.b.ready := Bool(true)
out.c.valid := Bool(false) out.c.valid := Bool(false)
@ -98,21 +100,21 @@ object TLRationalCrossingSource
object TLRationalCrossingSink object TLRationalCrossingSink
{ {
// applied to the TL source node; y.node := TLRationalCrossingSink()(x.node) // applied to the TL source node; y.node := TLRationalCrossingSink()(x.node)
def apply()(x: TLRationalOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = { def apply(direction: RationalDirection = Symmetric)(x: TLRationalOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
val sink = LazyModule(new TLRationalCrossingSink) val sink = LazyModule(new TLRationalCrossingSink(direction))
sink.node := x sink.node := x
sink.node sink.node
} }
} }
class TLRationalCrossing(implicit p: Parameters) extends LazyModule class TLRationalCrossing(direction: RationalDirection = Symmetric)(implicit p: Parameters) extends LazyModule
{ {
val nodeIn = TLInputNode() val nodeIn = TLInputNode()
val nodeOut = TLOutputNode() val nodeOut = TLOutputNode()
val node = NodeHandle(nodeIn, nodeOut) val node = NodeHandle(nodeIn, nodeOut)
val source = LazyModule(new TLRationalCrossingSource) val source = LazyModule(new TLRationalCrossingSource)
val sink = LazyModule(new TLRationalCrossingSink) val sink = LazyModule(new TLRationalCrossingSink(direction))
val _ = (sink.node := source.node) // no monitor val _ = (sink.node := source.node) // no monitor
val in = (source.node := nodeIn) val in = (source.node := nodeIn)
@ -150,7 +152,7 @@ import unittest._
class TLRAMRationalCrossing(implicit p: Parameters) extends LazyModule { class TLRAMRationalCrossing(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(5000)) val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel) val model = LazyModule(new TLRAMModel)
val cross = LazyModule(new TLRationalCrossing) val cross = LazyModule(new TLRationalCrossing(FastToSlow))
val delay = LazyModule(new TLDelayer(0.25)) val delay = LazyModule(new TLDelayer(0.25))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))

2
src/main/scala/uncore/tilelink2/package.scala
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@ -10,7 +10,7 @@ package object tilelink2
type TLInwardNode = InwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle] type TLInwardNode = InwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle]
type TLOutwardNode = OutwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle] type TLOutwardNode = OutwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle]
type TLAsyncOutwardNode = OutwardNodeHandle[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle] type TLAsyncOutwardNode = OutwardNodeHandle[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]
type TLRationalOutwardNode = OutwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLRationalBundle] type TLRationalOutwardNode = OutwardNodeHandle[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]
type IntOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]] type IntOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
def OH1ToOH(x: UInt) = (x << 1 | UInt(1)) & ~Cat(UInt(0, width=1), x) def OH1ToOH(x: UInt) = (x << 1 | UInt(1)) & ~Cat(UInt(0, width=1), x)