From 924afebbd997e8351d5f33fb74dfcd82eb1c2084 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 17 Feb 2017 04:19:00 +0100 Subject: [PATCH] tilelink2: make TLRational have configurable direction --- src/main/scala/uncore/tilelink2/Nodes.scala | 29 +++++++-------- .../scala/uncore/tilelink2/Parameters.scala | 9 +++++ .../uncore/tilelink2/RationalCrossing.scala | 36 ++++++++++--------- src/main/scala/uncore/tilelink2/package.scala | 2 +- 4 files changed, 44 insertions(+), 32 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/Nodes.scala b/src/main/scala/uncore/tilelink2/Nodes.scala index 82044873..22701f12 100644 --- a/src/main/scala/uncore/tilelink2/Nodes.scala +++ b/src/main/scala/uncore/tilelink2/Nodes.scala @@ -7,6 +7,7 @@ import chisel3.internal.sourceinfo.SourceInfo import config._ import diplomacy._ import scala.collection.mutable.ListBuffer +import util.RationalDirection case object TLMonitorBuilder extends Field[TLMonitorArgs => Option[TLMonitorBase]] case object TLFuzzReadyValid extends Field[Boolean] @@ -182,20 +183,20 @@ case class TLAsyncSinkNode(depth: Int, sync: Int) dFn = { p => p.base.copy(minLatency = sync+1) }, uFn = { p => TLAsyncManagerPortParameters(depth, p) }) -object TLRationalImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeParameters, TLEdgeParameters, TLRationalBundle] +object TLRationalImp extends NodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalEdgeParameters, TLRationalBundle] { - def edgeO(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeParameters = TLEdgeParameters(pd, pu) - def edgeI(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeParameters = TLEdgeParameters(pd, pu) + def edgeO(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu) + def edgeI(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu) - def bundleO(eo: Seq[TLEdgeParameters]): Vec[TLRationalBundle] = Vec(eo.size, new TLRationalBundle(TLBundleParameters.union(eo.map(_.bundle)))) - def bundleI(ei: Seq[TLEdgeParameters]): Vec[TLRationalBundle] = Vec(ei.size, new TLRationalBundle(TLBundleParameters.union(ei.map(_.bundle)))) + def bundleO(eo: Seq[TLRationalEdgeParameters]): Vec[TLRationalBundle] = Vec(eo.size, new TLRationalBundle(TLBundleParameters.union(eo.map(_.bundle)))) + def bundleI(ei: Seq[TLRationalEdgeParameters]): Vec[TLRationalBundle] = Vec(ei.size, new TLRationalBundle(TLBundleParameters.union(ei.map(_.bundle)))) def colour = "#00ff00" // green - override def mixO(pd: TLClientPortParameters, node: OutwardNode[TLClientPortParameters, TLManagerPortParameters, TLRationalBundle]): TLClientPortParameters = - pd.copy(clients = pd.clients.map { c => c.copy (nodePath = node +: c.nodePath) }) - override def mixI(pu: TLManagerPortParameters, node: InwardNode[TLClientPortParameters, TLManagerPortParameters, TLRationalBundle]): TLManagerPortParameters = - pu.copy(managers = pu.managers.map { m => m.copy (nodePath = node +: m.nodePath) }) + override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = + pd.copy(base = pd.base.copy(clients = pd.base.clients.map { c => c.copy (nodePath = node +: c.nodePath) })) + override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = + pu.copy(base = pu.base.copy(managers = pu.base.managers.map { m => m.copy (nodePath = node +: m.nodePath) })) } case class TLRationalIdentityNode() extends IdentityNode(TLRationalImp) @@ -204,10 +205,10 @@ case class TLRationalInputNode() extends InputNode(TLRationalImp) case class TLRationalSourceNode() extends MixedAdapterNode(TLImp, TLRationalImp)( - dFn = { p => p }, - uFn = { p => p.copy(minLatency = 1) }) // discard cycles from other clock domain + dFn = { p => TLRationalClientPortParameters(p) }, + uFn = { p => p.base.copy(minLatency = 1) }) // discard cycles from other clock domain -case class TLRationalSinkNode() +case class TLRationalSinkNode(direction: RationalDirection) extends MixedAdapterNode(TLRationalImp, TLImp)( - dFn = { p => p.copy(minLatency = 1) }, - uFn = { p => p }) + dFn = { p => p.base.copy(minLatency = 1) }, + uFn = { p => TLRationalManagerPortParameters(direction, p) }) diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala index 21b7a241..3462e559 100644 --- a/src/main/scala/uncore/tilelink2/Parameters.scala +++ b/src/main/scala/uncore/tilelink2/Parameters.scala @@ -5,6 +5,7 @@ package uncore.tilelink2 import Chisel._ import diplomacy._ import scala.math.max +import util.RationalDirection case class TLManagerParameters( address: Seq[AddressSet], @@ -326,6 +327,14 @@ case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: T val bundle = TLAsyncBundleParameters(manager.depth, TLBundleParameters(client.base, manager.base)) } +case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLManagerPortParameters) +case class TLRationalClientPortParameters(base: TLClientPortParameters) + +case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters) +{ + val bundle = TLBundleParameters(client.base, manager.base) +} + object ManagerUnification { def apply(managers: Seq[TLManagerParameters]) = { diff --git a/src/main/scala/uncore/tilelink2/RationalCrossing.scala b/src/main/scala/uncore/tilelink2/RationalCrossing.scala index 6d3b70fd..8a3b0b64 100644 --- a/src/main/scala/uncore/tilelink2/RationalCrossing.scala +++ b/src/main/scala/uncore/tilelink2/RationalCrossing.scala @@ -27,14 +27,15 @@ class TLRationalCrossingSource(implicit p: Parameters) extends LazyModule ((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) => val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe + val direction = edgeOut.manager.direction - out.a <> ToRational(in.a) - in.d <> FromRational(out.d) + out.a <> ToRational(in.a, direction) + in.d <> FromRational(out.d, direction.flip) if (bce) { - in.b <> FromRational(out.b) - out.c <> ToRational(in.c) - out.e <> ToRational(in.e) + in.b <> FromRational(out.b, direction.flip) + out.c <> ToRational(in.c, direction) + out.e <> ToRational(in.e, direction) } else { in.b.valid := Bool(false) in.c.ready := Bool(true) @@ -50,9 +51,9 @@ class TLRationalCrossingSource(implicit p: Parameters) extends LazyModule } } -class TLRationalCrossingSink(implicit p: Parameters) extends LazyModule +class TLRationalCrossingSink(direction: RationalDirection = Symmetric)(implicit p: Parameters) extends LazyModule { - val node = TLRationalSinkNode() + val node = TLRationalSinkNode(direction) lazy val module = new LazyModuleImp(this) { val io = new Bundle { @@ -62,14 +63,15 @@ class TLRationalCrossingSink(implicit p: Parameters) extends LazyModule ((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) => val bce = edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe + val direction = edgeIn.manager.direction - out.a <> FromRational(in.a) - in.d <> ToRational(out.d) + out.a <> FromRational(in.a, direction) + in.d <> ToRational(out.d, direction.flip) if (bce) { - in.b <> ToRational(out.b) - out.c <> FromRational(in.c) - out.e <> FromRational(in.e) + in.b <> ToRational(out.b, direction.flip) + out.c <> FromRational(in.c, direction) + out.e <> FromRational(in.e, direction) } else { out.b.ready := Bool(true) out.c.valid := Bool(false) @@ -98,21 +100,21 @@ object TLRationalCrossingSource object TLRationalCrossingSink { // applied to the TL source node; y.node := TLRationalCrossingSink()(x.node) - def apply()(x: TLRationalOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = { - val sink = LazyModule(new TLRationalCrossingSink) + def apply(direction: RationalDirection = Symmetric)(x: TLRationalOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = { + val sink = LazyModule(new TLRationalCrossingSink(direction)) sink.node := x sink.node } } -class TLRationalCrossing(implicit p: Parameters) extends LazyModule +class TLRationalCrossing(direction: RationalDirection = Symmetric)(implicit p: Parameters) extends LazyModule { val nodeIn = TLInputNode() val nodeOut = TLOutputNode() val node = NodeHandle(nodeIn, nodeOut) val source = LazyModule(new TLRationalCrossingSource) - val sink = LazyModule(new TLRationalCrossingSink) + val sink = LazyModule(new TLRationalCrossingSink(direction)) val _ = (sink.node := source.node) // no monitor val in = (source.node := nodeIn) @@ -150,7 +152,7 @@ import unittest._ class TLRAMRationalCrossing(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(5000)) val model = LazyModule(new TLRAMModel) - val cross = LazyModule(new TLRationalCrossing) + val cross = LazyModule(new TLRationalCrossing(FastToSlow)) val delay = LazyModule(new TLDelayer(0.25)) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) diff --git a/src/main/scala/uncore/tilelink2/package.scala b/src/main/scala/uncore/tilelink2/package.scala index f382ebdf..026b592d 100644 --- a/src/main/scala/uncore/tilelink2/package.scala +++ b/src/main/scala/uncore/tilelink2/package.scala @@ -10,7 +10,7 @@ package object tilelink2 type TLInwardNode = InwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle] type TLOutwardNode = OutwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle] type TLAsyncOutwardNode = OutwardNodeHandle[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle] - type TLRationalOutwardNode = OutwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLRationalBundle] + type TLRationalOutwardNode = OutwardNodeHandle[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle] type IntOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]] def OH1ToOH(x: UInt) = (x << 1 | UInt(1)) & ~Cat(UInt(0, width=1), x)