riscv/rocket-chip
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Merge remote-tracking branch 'origin/master' into ss-frontend

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Also fixed bridx logic and zero-width wire logic.

Conflicts:
	src/main/scala/btb.scala
This commit is contained in:
Christopher Celio
2014-10-14 18:10:29 -07:00
parent 59eb7d194d 7bb7299018
commit 91efdc379b
4 changed files with 19 additions and 17 deletions
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rocket/src/main/scala/icache.scala
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@ -114,7 +114,7 @@ class Frontend extends FrontendModule
}
val all_ones = UInt((1 << coreFetchWidth)-1)
val msk_pc = all_ones << s2_pc(log2Up(coreFetchWidth)-1+2,2)
val msk_pc = if (coreFetchWidth == 1) all_ones else all_ones << s2_pc(log2Up(coreFetchWidth) -1+2,2)
io.cpu.resp.bits.mask := msk_pc & btb.io.resp.bits.mask
io.cpu.resp.bits.xcpt_ma := s2_pc(log2Up(coreInstBytes)-1,0) != UInt(0)