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ClockDivider: add docs to appease the reviewer

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... even though this means a delay of 1:30 hours :(
This commit is contained in:
Wesley W. Terpstra 2017-02-17 19:34:44 +01:00
parent 3931b0faff
commit 9153a9a733
2 changed files with 13 additions and 2 deletions
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10
src/main/scala/util/ClockDivider.scala
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@ -4,7 +4,15 @@ package util
import Chisel._
/** Divide the clock by 2 */
/** This black-boxes a Clock Divider by 2.
* The output clock is phase-aligned to the input clock.
* If you use this in synthesis, make sure your sdc
* declares that you want it to do the same.
*
* Because Chisel does not support
* blocking assignments, it is impossible
* to create a deterministic divided clock.
*/
class ClockDivider2 extends BlackBox {
val io = new Bundle {
val clk_out = Clock(OUTPUT)

5
vsrc/ClockDivider2.v
View File

@ -1,6 +1,9 @@
// See LICENSE.SiFive for license details.
/** This black-boxes a Clock Divider.
/** This black-boxes a Clock Divider by 2.
* The output clock is phase-aligned to the input clock.
* If you use this in synthesis, make sure your sdc
* declares that you want it to do the same.
*
* Because Chisel does not support
* blocking assignments, it is impossible