From 9153a9a7335f319a8d45f912898c4d8695168e08 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 17 Feb 2017 19:34:44 +0100 Subject: [PATCH] ClockDivider: add docs to appease the reviewer ... even though this means a delay of 1:30 hours :( --- src/main/scala/util/ClockDivider.scala | 10 +++++++++- vsrc/ClockDivider2.v | 5 ++++- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/src/main/scala/util/ClockDivider.scala b/src/main/scala/util/ClockDivider.scala index 094f045f..bbe07279 100644 --- a/src/main/scala/util/ClockDivider.scala +++ b/src/main/scala/util/ClockDivider.scala @@ -4,7 +4,15 @@ package util import Chisel._ -/** Divide the clock by 2 */ +/** This black-boxes a Clock Divider by 2. + * The output clock is phase-aligned to the input clock. + * If you use this in synthesis, make sure your sdc + * declares that you want it to do the same. + * + * Because Chisel does not support + * blocking assignments, it is impossible + * to create a deterministic divided clock. + */ class ClockDivider2 extends BlackBox { val io = new Bundle { val clk_out = Clock(OUTPUT) diff --git a/vsrc/ClockDivider2.v b/vsrc/ClockDivider2.v index 9da5e93c..b1190d33 100644 --- a/vsrc/ClockDivider2.v +++ b/vsrc/ClockDivider2.v @@ -1,6 +1,9 @@ // See LICENSE.SiFive for license details. -/** This black-boxes a Clock Divider. +/** This black-boxes a Clock Divider by 2. + * The output clock is phase-aligned to the input clock. + * If you use this in synthesis, make sure your sdc + * declares that you want it to do the same. * * Because Chisel does not support * blocking assignments, it is impossible