riscv/rocket-chip
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coreplex: first cut at using RocketCrossingParams

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This commit is contained in:
Henry Cook
2017-10-09 23:43:18 -07:00
parent d6766a8c68
commit 9026646459
8 changed files with 65 additions and 41 deletions
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2
src/main/scala/groundtest/Coreplex.scala
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@ -25,7 +25,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
})
)}
tiles.flatMap(_.dcacheOpt).foreach { sbus.fromSyncTiles(BufferParams.default) :=* _.node }
tiles.flatMap(_.dcacheOpt).foreach { sbus.fromSyncTiles(BufferParams.default, TilePortParams()) :=* _.node }
val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, pbus.beatBytes))
pbusRAM.node := pbus.toVariableWidthSlaves

4
src/main/scala/groundtest/Tile.scala
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@ -7,7 +7,7 @@ import Chisel._
import freechips.rocketchip.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.coreplex._
import freechips.rocketchip.rocket.{HellaCache, RocketCoreParams}
import freechips.rocketchip.rocket.{DCache, RocketCoreParams}
import freechips.rocketchip.tile._
import scala.collection.mutable.ListBuffer
@ -30,7 +30,7 @@ case object GroundTestTilesKey extends Field[Seq[GroundTestTileParams]]
abstract class GroundTestTile(params: GroundTestTileParams)(implicit p: Parameters) extends BaseTile(params)(p) {
val slave = None
val dcacheOpt = params.dcache.map { dc => LazyModule(HellaCache(0, dc.nMSHRs == 0)) }
val dcacheOpt = params.dcache.map { dc => LazyModule(new DCache(0)) }
override lazy val module = new GroundTestTileModule(this, () => new GroundTestTileBundle(this))
}