diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala index 0d932c04..c9f6c797 100644 --- a/src/main/scala/coreplex/Configs.scala +++ b/src/main/scala/coreplex/Configs.scala @@ -242,15 +242,21 @@ class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => { }) class WithSynchronousRocketTiles extends Config((site, here, up) => { - case RocketCrossing => SynchronousCrossing() + case RocketCrossingKey => up(RocketCrossingKey, site) map { r => + r.copy(crossingType = SynchronousCrossing()) + } }) class WithAynchronousRocketTiles(depth: Int, sync: Int) extends Config((site, here, up) => { - case RocketCrossing => AsynchronousCrossing(depth, sync) + case RocketCrossingKey => up(RocketCrossingKey, site) map { r => + r.copy(crossingType = AsynchronousCrossing(depth, sync)) + } }) class WithRationalRocketTiles extends Config((site, here, up) => { - case RocketCrossing => RationalCrossing() + case RocketCrossingKey => up(RocketCrossingKey, site) map { r => + r.copy(crossingType = RationalCrossing()) + } }) class WithEdgeDataBits(dataBits: Int) extends Config((site, here, up) => { diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala index fa315ddb..93e6544e 100644 --- a/src/main/scala/coreplex/RocketCoreplex.scala +++ b/src/main/scala/coreplex/RocketCoreplex.scala @@ -11,8 +11,23 @@ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ +// TODO: how specific are these to RocketTiles? +case class TilePortParams( + addBuffers: Int = 0, + blockerCtrlAddr: Option[BigInt] = None) + +case class RocketCrossingParams( + crossingType: CoreplexClockCrossing = SynchronousCrossing(), + master: TilePortParams = TilePortParams(), + slave: TilePortParams = TilePortParams()) { + def knownRatio: Option[Int] = crossingType match { + case RationalCrossing(_) => Some(2) + case _ => None + } +} + case object RocketTilesKey extends Field[Seq[RocketTileParams]](Nil) -case object RocketCrossing extends Field[CoreplexClockCrossing](SynchronousCrossing()) +case object RocketCrossingKey extends Field[Seq[RocketCrossingParams]](List(RocketCrossingParams())) trait HasRocketTiles extends HasTiles with HasPeripheryBus @@ -21,35 +36,43 @@ trait HasRocketTiles extends HasTiles with HasPeripheryDebug { val module: HasRocketTilesModuleImp - private val crossing = p(RocketCrossing) protected val tileParams = p(RocketTilesKey) + private val NumRocketTiles = tileParams.size + private val crossingParams = p(RocketCrossingKey) + private val crossings = crossingParams.size match { + case 1 => List.fill(NumRocketTiles) { crossingParams.head } + case NumRocketTiles => crossingParams + case _ => throw new Exception("RocketCrossingKey.size must == 1 or == RocketTilesKey.size") + } // Make a wrapper for each tile that will wire it to coreplex devices and crossbars, // according to the specified type of clock crossing. - val tiles: Seq[BaseTile] = localIntNodes.zip(tileParams).map { case (lip, tp) => + private val crossingTuples = localIntNodes.zip(tileParams).zip(crossings) + val tiles: Seq[BaseTile] = crossingTuples.map { case ((lip, tp), crossing) => val pWithExtra = p.alterPartial { case TileKey => tp case BuildRoCC => tp.rocc case SharedMemoryTLEdge => sharedMemoryTLEdge + case RocketCrossingKey => List(crossing) } - val wrapper = crossing match { + val wrapper = crossing.crossingType match { case SynchronousCrossing(params) => { val wrapper = LazyModule(new SyncRocketTile(tp)(pWithExtra)) - sbus.fromSyncTiles(params, tp.externalMasterBuffers, tp.name) :=* wrapper.masterNode - FlipRendering { implicit p => wrapper.slaveNode :*= pbus.toSyncSlaves(tp.name, tp.externalSlaveBuffers) } + sbus.fromSyncTiles(params, crossing.master, tp.name) :=* wrapper.masterNode + FlipRendering { implicit p => wrapper.slaveNode :*= pbus.toSyncSlaves(tp.name, crossing.slave.addBuffers) } wrapper } case AsynchronousCrossing(depth, sync) => { val wrapper = LazyModule(new AsyncRocketTile(tp)(pWithExtra)) - sbus.fromAsyncTiles(depth, sync, tp.externalMasterBuffers, tp.name) :=* wrapper.masterNode - FlipRendering { implicit p => wrapper.slaveNode :*= pbus.toAsyncSlaves(sync, tp.name, tp.externalSlaveBuffers) } + sbus.fromAsyncTiles(depth, sync, crossing.master, tp.name) :=* wrapper.masterNode + FlipRendering { implicit p => wrapper.slaveNode :*= pbus.toAsyncSlaves(sync, tp.name, crossing.slave.addBuffers) } wrapper } case RationalCrossing(direction) => { val wrapper = LazyModule(new RationalRocketTile(tp)(pWithExtra)) - sbus.fromRationalTiles(direction, tp.externalMasterBuffers, tp.name) :=* wrapper.masterNode - FlipRendering { implicit p => wrapper.slaveNode :*= pbus.toRationalSlaves(tp.name, tp.externalSlaveBuffers) } + sbus.fromRationalTiles(direction, crossing.master, tp.name) :=* wrapper.masterNode + FlipRendering { implicit p => wrapper.slaveNode :*= pbus.toRationalSlaves(tp.name, crossing.slave.addBuffers) } wrapper } } diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala index 7096b3e5..a755662e 100644 --- a/src/main/scala/coreplex/SystemBus.scala +++ b/src/main/scala/coreplex/SystemBus.scala @@ -55,30 +55,31 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr def fromFrontBus: TLInwardNode = master_splitter.node - def fromSyncTiles(params: BufferParams, addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = { + def fromSyncTiles(params: BufferParams, port: TilePortParams, name: Option[String] = None): TLInwardNode = { val tile_buf = LazyModule(new TLBuffer(params)) name.foreach { n => tile_buf.suggestName(s"${busName}_${n}_TLBuffer") } - val (in, out) = bufferChain(addBuffers, name = name) + val (in, out) = bufferChain(port.addBuffers, name = name) tile_fixer.node :=* out in :=* tile_buf.node tile_buf.node } - def fromRationalTiles(dir: RationalDirection, addBuffers: Int = 0, name: Option[String] = None): TLRationalInwardNode = { + def fromRationalTiles(dir: RationalDirection, port: TilePortParams, name: Option[String] = None): TLRationalInwardNode = { + // TODO val tile_blocker = port.blockerCtrlAddr.map(a => LazyModule(new BusBlocker(BusBlockerParams(a, , )))) val tile_sink = LazyModule(new TLRationalCrossingSink(direction = dir)) name.foreach { n => tile_sink.suggestName(s"${busName}_${n}_TLRationalCrossingSink") } - val (in, out) = bufferChain(addBuffers, name = name) + val (in, out) = bufferChain(port.addBuffers, name = name) tile_fixer.node :=* out in :=* tile_sink.node tile_sink.node } - def fromAsyncTiles(depth: Int, sync: Int, addBuffers: Int = 0, name: Option[String] = None): TLAsyncInwardNode = { + def fromAsyncTiles(depth: Int, sync: Int, port: TilePortParams, name: Option[String] = None): TLAsyncInwardNode = { val tile_sink = LazyModule(new TLAsyncCrossingSink(depth, sync)) name.foreach { n => tile_sink.suggestName(s"${busName}_${n}_TLAsyncCrossingSink") } - val (in, out) = bufferChain(addBuffers, name = name) + val (in, out) = bufferChain(port.addBuffers, name = name) tile_fixer.node :=* out in :=* tile_sink.node diff --git a/src/main/scala/groundtest/Coreplex.scala b/src/main/scala/groundtest/Coreplex.scala index d6dab576..e45dbc3f 100644 --- a/src/main/scala/groundtest/Coreplex.scala +++ b/src/main/scala/groundtest/Coreplex.scala @@ -25,7 +25,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex }) )} - tiles.flatMap(_.dcacheOpt).foreach { sbus.fromSyncTiles(BufferParams.default) :=* _.node } + tiles.flatMap(_.dcacheOpt).foreach { sbus.fromSyncTiles(BufferParams.default, TilePortParams()) :=* _.node } val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, pbus.beatBytes)) pbusRAM.node := pbus.toVariableWidthSlaves diff --git a/src/main/scala/groundtest/Tile.scala b/src/main/scala/groundtest/Tile.scala index 573e71c6..ccb8b853 100644 --- a/src/main/scala/groundtest/Tile.scala +++ b/src/main/scala/groundtest/Tile.scala @@ -7,7 +7,7 @@ import Chisel._ import freechips.rocketchip.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.coreplex._ -import freechips.rocketchip.rocket.{HellaCache, RocketCoreParams} +import freechips.rocketchip.rocket.{DCache, RocketCoreParams} import freechips.rocketchip.tile._ import scala.collection.mutable.ListBuffer @@ -30,7 +30,7 @@ case object GroundTestTilesKey extends Field[Seq[GroundTestTileParams]] abstract class GroundTestTile(params: GroundTestTileParams)(implicit p: Parameters) extends BaseTile(params)(p) { val slave = None - val dcacheOpt = params.dcache.map { dc => LazyModule(HellaCache(0, dc.nMSHRs == 0)) } + val dcacheOpt = params.dcache.map { dc => LazyModule(new DCache(0)) } override lazy val module = new GroundTestTileModule(this, () => new GroundTestTileBundle(this)) } diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index e3daa973..ed872a2a 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -5,7 +5,7 @@ package freechips.rocketchip.rocket import Chisel._ import Chisel.ImplicitConversions._ import freechips.rocketchip.config.Parameters -import freechips.rocketchip.coreplex.{RationalCrossing, RocketCrossing, RocketTilesKey} +import freechips.rocketchip.coreplex.{RocketTilesKey} import freechips.rocketchip.diplomacy.{AddressSet, RegionType} import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ @@ -62,7 +62,7 @@ class DCacheMetadataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) val data = new L1Metadata } -class DCache(hartid: Int, val scratch: () => Option[AddressSet] = () => None)(implicit p: Parameters) extends HellaCache(hartid)(p) { +class DCache(hartid: Int, val scratch: () => Option[AddressSet] = () => None, val bufferUncachedRequests: Option[Int] = None)(implicit p: Parameters) extends HellaCache(hartid)(p) { override lazy val module = new DCacheModule(this) } @@ -89,14 +89,12 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { dataArb.io.out.ready := true metaArb.io.out.ready := true - val rational = p(RocketCrossing) match { - case RationalCrossing(_) => true - case _ => false - } - - val q_depth = if (rational) (2 min maxUncachedInFlight-1) else 0 val tl_out_a = Wire(tl_out.a) - tl_out.a <> (if (q_depth == 0) tl_out_a else Queue(tl_out_a, q_depth, flow = true)) + tl_out.a <> outer.bufferUncachedRequests + .map(_ min maxUncachedInFlight-1) + .map(Queue(tl_out_a, _, flow = true)) + .getOrElse(tl_out_a) + val (tl_out_c, release_queue_empty) = if (cacheParams.acquireBeforeRelease) { val q = Module(new Queue(tl_out.c.bits, cacheDataBeats, flow = true)) diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala index 558e0259..4648a4b9 100644 --- a/src/main/scala/rocket/HellaCache.scala +++ b/src/main/scala/rocket/HellaCache.scala @@ -192,12 +192,6 @@ class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) } } -object HellaCache { - def apply(hartid: Int, blocking: Boolean, scratch: () => Option[AddressSet] = () => None)(implicit p: Parameters) = { - if (blocking) new DCache(hartid, scratch) else new NonBlockingDCache(hartid) - } -} - /** Mix-ins for constructing tiles that have a HellaCache */ trait HasHellaCache extends HasTileLinkMasterPort with HasTileParameters { @@ -206,7 +200,11 @@ trait HasHellaCache extends HasTileLinkMasterPort with HasTileParameters { def findScratchpadFromICache: Option[AddressSet] val hartid: Int var nDCachePorts = 0 - val dcache = LazyModule(HellaCache(hartid, tileParams.dcache.get.nMSHRs == 0, findScratchpadFromICache _)) + val dcache: HellaCache = LazyModule( + if(tileParams.dcache.get.nMSHRs == 0) { + new DCache(hartid, findScratchpadFromICache _, p(RocketCrossingKey).head.knownRatio) + } else { new NonBlockingDCache(hartid) }) + tileBus.node := dcache.node } diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala index 89eda305..fde37ab6 100644 --- a/src/main/scala/tile/RocketTile.scala +++ b/src/main/scala/tile/RocketTile.scala @@ -22,9 +22,7 @@ case class RocketTileParams( trace: Boolean = false, hcfOnUncorrectable: Boolean = false, name: Option[String] = Some("tile"), - hartid: Int = 0, - externalMasterBuffers: Int = 0, - externalSlaveBuffers: Int = 0) extends TileParams { + hartid: Int = 0) extends TileParams { require(icache.isDefined) require(dcache.isDefined) }