riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Removed unnecessary signal in CSRIO

Browse Source
This commit is contained in:
Christopher Celio 2015-04-11 02:20:34 -07:00
parent 2f88c5ca9d
commit 8fc2d38ca9
1 changed files with 0 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
rocket/src/main/scala/csr.scala
View File

@ -93,7 +93,6 @@ class CSRFileIO extends CoreBundle {
val uarch_counters = Vec.fill(16)(UInt(INPUT, log2Up(1+retireWidth))) val uarch_counters = Vec.fill(16)(UInt(INPUT, log2Up(1+retireWidth)))
val custom_mrw_csrs = Vec.fill(params(NCustomMRWCSRs))(UInt(INPUT, xLen)) val custom_mrw_csrs = Vec.fill(params(NCustomMRWCSRs))(UInt(INPUT, xLen))
val cause = UInt(INPUT, xLen) val cause = UInt(INPUT, xLen)
val mbadaddr_wen = Bool(INPUT)
val pc = SInt(INPUT, vaddrBits+1) val pc = SInt(INPUT, vaddrBits+1)
val fatc = Bool(OUTPUT) val fatc = Bool(OUTPUT)
val time = UInt(OUTPUT, xLen) val time = UInt(OUTPUT, xLen)