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axi4: IdIndexer; a single ID does NOT imply no response interleaving

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Some slaves may never send R until you process their B.
Thus, while there is no read response interleaving, there
is still interleaving between R and B, which breaks AXI4ToTL.
This commit is contained in:
Wesley W. Terpstra 2017-05-08 00:03:07 -07:00
parent 4847c32599
commit 8fc27b0bf2
2 changed files with 2 additions and 4 deletions
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4
src/main/scala/uncore/axi4/IdIndexer.scala
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@ -34,9 +34,7 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
userBits = mp.userBits + max(0, log2Ceil(mp.endId) - idBits), userBits = mp.userBits + max(0, log2Ceil(mp.endId) - idBits),
masters = masters) masters = masters)
}, },
slaveFn = { sp => sp.copy( slaveFn = { sp => sp
slaves = sp.slaves.map(s => s.copy(
interleavedId = if (idBits == 0) Some(0) else s.interleavedId)))
}) })
lazy val module = new LazyModuleImp(this) { lazy val module = new LazyModuleImp(this) {

2
src/main/scala/uncore/axi4/Parameters.scala
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@ -15,7 +15,7 @@ case class AXI4SlaveParameters(
nodePath: Seq[BaseNode] = Seq(), nodePath: Seq[BaseNode] = Seq(),
supportsWrite: TransferSizes = TransferSizes.none, supportsWrite: TransferSizes = TransferSizes.none,
supportsRead: TransferSizes = TransferSizes.none, supportsRead: TransferSizes = TransferSizes.none,
interleavedId: Option[Int] = None) // The device will not interleave read responses interleavedId: Option[Int] = None) // The device will not interleave responses (R+B)
{ {
address.foreach { a => require (a.finite) } address.foreach { a => require (a.finite) }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap") }