From 8fc27b0bf21cfaaf50425a802bdb786f79f8c7ad Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Mon, 8 May 2017 00:03:07 -0700 Subject: [PATCH] axi4: IdIndexer; a single ID does NOT imply no response interleaving Some slaves may never send R until you process their B. Thus, while there is no read response interleaving, there is still interleaving between R and B, which breaks AXI4ToTL. --- src/main/scala/uncore/axi4/IdIndexer.scala | 4 +--- src/main/scala/uncore/axi4/Parameters.scala | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/main/scala/uncore/axi4/IdIndexer.scala b/src/main/scala/uncore/axi4/IdIndexer.scala index 8abf78db..e999a200 100644 --- a/src/main/scala/uncore/axi4/IdIndexer.scala +++ b/src/main/scala/uncore/axi4/IdIndexer.scala @@ -34,9 +34,7 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule userBits = mp.userBits + max(0, log2Ceil(mp.endId) - idBits), masters = masters) }, - slaveFn = { sp => sp.copy( - slaves = sp.slaves.map(s => s.copy( - interleavedId = if (idBits == 0) Some(0) else s.interleavedId))) + slaveFn = { sp => sp }) lazy val module = new LazyModuleImp(this) { diff --git a/src/main/scala/uncore/axi4/Parameters.scala b/src/main/scala/uncore/axi4/Parameters.scala index 8642613e..6b4a0c2e 100644 --- a/src/main/scala/uncore/axi4/Parameters.scala +++ b/src/main/scala/uncore/axi4/Parameters.scala @@ -15,7 +15,7 @@ case class AXI4SlaveParameters( nodePath: Seq[BaseNode] = Seq(), supportsWrite: TransferSizes = TransferSizes.none, supportsRead: TransferSizes = TransferSizes.none, - interleavedId: Option[Int] = None) // The device will not interleave read responses + interleavedId: Option[Int] = None) // The device will not interleave responses (R+B) { address.foreach { a => require (a.finite) } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap") }