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UInt-> Bits; avoid mixed UInt/SInt code

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This commit is contained in:
Andrew Waterman 2015-07-30 23:46:32 -07:00
parent 6c391e3b37
commit 8f7b390353
2 changed files with 5 additions and 5 deletions
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6
uncore/src/main/scala/cache.scala
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@ -36,7 +36,7 @@ abstract trait CacheParameters extends UsesParameters {
abstract class CacheBundle extends Bundle with CacheParameters
abstract class CacheModule extends Module with CacheParameters
class StoreGen(typ: Bits, addr: Bits, dat: Bits) {
class StoreGen(typ: UInt, addr: UInt, dat: UInt) {
val byte = typ === MT_B || typ === MT_BU
val half = typ === MT_H || typ === MT_HU
val word = typ === MT_W || typ === MT_WU
@ -54,7 +54,7 @@ class StoreGen(typ: Bits, addr: Bits, dat: Bits) {
dat)
}
class LoadGen(typ: Bits, addr: Bits, dat: Bits, zero: Bool) {
class LoadGen(typ: UInt, addr: UInt, dat: UInt, zero: Bool) {
val t = new StoreGen(typ, addr, dat)
val sign = typ === MT_B || typ === MT_H || typ === MT_W || typ === MT_D
@ -87,7 +87,7 @@ class AMOALU extends CacheModule {
val word = io.typ === MT_W || io.typ === MT_WU || // Logic minimization:
io.typ === MT_B || io.typ === MT_BU
val mask = SInt(-1,64) ^ (io.addr(2) << UInt(31))
val mask = ~UInt(0,64) ^ (io.addr(2) << UInt(31))
val adder_out = (io.lhs & mask).toUInt + (rhs & mask)
val cmp_lhs = Mux(word && !io.addr(2), io.lhs(31), io.lhs(63))

4
uncore/src/main/scala/ecc.scala
View File

@ -107,11 +107,11 @@ class SECDEDCode extends Code
object ErrGen
{
// generate a 1-bit error with approximate probability 2^-f
def apply(width: Int, f: Int): Bits = {
def apply(width: Int, f: Int): UInt = {
require(width > 0 && f >= 0 && log2Up(width) + f <= 16)
UIntToOH(LFSR16()(log2Up(width)+f-1,0))(width-1,0)
}
def apply(x: Bits, f: Int): Bits = x ^ apply(x.getWidth, f)
def apply(x: UInt, f: Int): UInt = x ^ apply(x.getWidth, f)
}
class SECDEDTest extends Module