From 8f7b3903538748e5b93f911be3b0aff737645990 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Thu, 30 Jul 2015 23:46:32 -0700
Subject: [PATCH] UInt-> Bits; avoid mixed UInt/SInt code

---
 uncore/src/main/scala/cache.scala | 6 +++---
 uncore/src/main/scala/ecc.scala   | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/uncore/src/main/scala/cache.scala b/uncore/src/main/scala/cache.scala
index b956a2e0..6e5872c2 100644
--- a/uncore/src/main/scala/cache.scala
+++ b/uncore/src/main/scala/cache.scala
@@ -36,7 +36,7 @@ abstract trait CacheParameters extends UsesParameters {
 abstract class CacheBundle extends Bundle with CacheParameters
 abstract class CacheModule extends Module with CacheParameters
 
-class StoreGen(typ: Bits, addr: Bits, dat: Bits) {
+class StoreGen(typ: UInt, addr: UInt, dat: UInt) {
   val byte = typ === MT_B || typ === MT_BU
   val half = typ === MT_H || typ === MT_HU
   val word = typ === MT_W || typ === MT_WU
@@ -54,7 +54,7 @@ class StoreGen(typ: Bits, addr: Bits, dat: Bits) {
                       dat)
 }
 
-class LoadGen(typ: Bits, addr: Bits, dat: Bits, zero: Bool) {
+class LoadGen(typ: UInt, addr: UInt, dat: UInt, zero: Bool) {
   val t = new StoreGen(typ, addr, dat)
   val sign = typ === MT_B || typ === MT_H || typ === MT_W || typ === MT_D
 
@@ -87,7 +87,7 @@ class AMOALU extends CacheModule {
   val word = io.typ === MT_W || io.typ === MT_WU || // Logic minimization:
                io.typ === MT_B || io.typ === MT_BU
 
-  val mask = SInt(-1,64) ^ (io.addr(2) << UInt(31))
+  val mask = ~UInt(0,64) ^ (io.addr(2) << UInt(31))
   val adder_out = (io.lhs & mask).toUInt + (rhs & mask)
 
   val cmp_lhs  = Mux(word && !io.addr(2), io.lhs(31), io.lhs(63))
diff --git a/uncore/src/main/scala/ecc.scala b/uncore/src/main/scala/ecc.scala
index b5864b2c..609e5fca 100644
--- a/uncore/src/main/scala/ecc.scala
+++ b/uncore/src/main/scala/ecc.scala
@@ -107,11 +107,11 @@ class SECDEDCode extends Code
 object ErrGen
 {
   // generate a 1-bit error with approximate probability 2^-f
-  def apply(width: Int, f: Int): Bits = {
+  def apply(width: Int, f: Int): UInt = {
     require(width > 0 && f >= 0 && log2Up(width) + f <= 16)
     UIntToOH(LFSR16()(log2Up(width)+f-1,0))(width-1,0)
   }
-  def apply(x: Bits, f: Int): Bits = x ^ apply(x.getWidth, f)
+  def apply(x: UInt, f: Int): UInt = x ^ apply(x.getWidth, f)
 }
 
 class SECDEDTest extends Module