riscv/rocket-chip
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stall for more cycles in Hasti test

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This commit is contained in:
Howard Mao 2016-05-31 19:46:42 -07:00
parent 2a7e7172a9
commit 8f269b2eec
1 changed files with 3 additions and 1 deletions
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4
groundtest/src/main/scala/unittest.scala
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@ -30,6 +30,8 @@ class HastiTestDriver(implicit p: Parameters) extends NastiModule {
s_read_addr :: s_read_data :: s_read_stall :: s_done :: Nil) = Enum(Bits(), 9) s_read_addr :: s_read_data :: s_read_stall :: s_done :: Nil) = Enum(Bits(), 9)
val state = Reg(init = s_idle) val state = Reg(init = s_idle)
val (stall_cnt, stall_done) = Counter(state === s_read_stall, 2)
io.nasti.aw.valid := (state === s_write_addr) io.nasti.aw.valid := (state === s_write_addr)
io.nasti.aw.bits := NastiWriteAddressChannel( io.nasti.aw.bits := NastiWriteAddressChannel(
id = UInt(0), id = UInt(0),
@ -63,7 +65,7 @@ class HastiTestDriver(implicit p: Parameters) extends NastiModule {
when (io.nasti.b.fire()) { state := s_read_addr } when (io.nasti.b.fire()) { state := s_read_addr }
when (io.nasti.ar.fire()) { state := s_read_data } when (io.nasti.ar.fire()) { state := s_read_data }
when (io.nasti.r.fire()) { state := s_read_stall } when (io.nasti.r.fire()) { state := s_read_stall }
when (state === s_read_stall) { state := s_read_data } when (stall_done) { state := s_read_data }
when (read_done) { state := s_done } when (read_done) { state := s_done }
val read_data = Mux(read_cnt(0), val read_data = Mux(read_cnt(0),