1
0

optionally export detailed status information in DirectGroundTest

This commit is contained in:
Howard Mao 2016-07-11 12:17:29 -07:00
parent b64998ec05
commit 8f0fa11ce4
4 changed files with 37 additions and 3 deletions

@ -1 +1 @@
Subproject commit f5d1a1b27bc369b9fed9c9f5fb3649f9e94edf6b
Subproject commit b0bc77c331ddb24558f9871135ba5bcbf8be2ac4

View File

@ -307,6 +307,7 @@ class BaseConfig extends Config (
case ConfigString => makeConfigString()
case GlobalAddrMap => globalAddrMap
case EnableL2Logging => false
case ExportGroundTestStatus => false
case _ => throw new CDEMatchError
}},
knobValues = {
@ -416,6 +417,7 @@ class WithRV32 extends Config(
class FPGAConfig extends Config (
(pname,site,here) => pname match {
case NAcquireTransactors => 4
case ExportGroundTestStatus => true
case _ => throw new CDEMatchError
}
)

View File

@ -6,10 +6,15 @@ import groundtest._
import uncore.tilelink._
import uncore.agents._
case object ExportGroundTestStatus extends Field[Boolean]
class DirectGroundTestTop(topParams: Parameters) extends Module
with HasTopLevelParameters {
implicit val p = topParams
val io = new TopIO
val io = new TopIO {
// Need to export this for FPGA testing, but not for simulator
val status = if (p(ExportGroundTestStatus)) Some(new GroundTestStatus) else None
}
// Not using the debug
io.debug.req.ready := Bool(false)
@ -28,7 +33,7 @@ class DirectGroundTestTop(topParams: Parameters) extends Module
require(test.io.mem.size == nBanksPerMemChannel)
require(test.io.ptw.size == 0)
when (test.io.finished) { stop() }
when (test.io.status.finished) { stop() }
val mem_ic = Module(new TileLinkMemoryInterconnect(
nBanksPerMemChannel, nMemChannels)(outermostParams))
@ -37,4 +42,26 @@ class DirectGroundTestTop(topParams: Parameters) extends Module
io.mem_axi.zip(mem_ic.io.out).foreach { case (nasti, tl) =>
TopUtils.connectTilelinkNasti(nasti, tl)(outermostParams)
}
io.status.map { status =>
val s_running :: s_finished :: s_errored :: s_timeout :: Nil = Enum(Bits(), 4)
val state = Reg(init = s_running)
val error_code = Reg(status.error.bits)
val timeout_code = Reg(status.timeout.bits)
when (state === s_running) {
when (test.io.status.finished) { state := s_finished }
when (test.io.status.error.valid) {
state := s_errored
error_code := test.io.status.error.bits
}
when (test.io.status.timeout.valid) {
state := s_timeout
timeout_code := test.io.status.timeout.bits
}
}
status.finished := (state === s_finished)
status.error.valid := (state === s_errored)
status.error.bits := error_code
status.timeout.valid := (state === s_timeout)
status.timeout.bits := timeout_code
}
}

View File

@ -300,3 +300,8 @@ class DirectMemtestConfig extends Config(
new WithDirectMemtest ++ new GroundTestConfig)
class DirectComparatorConfig extends Config(
new WithDirectComparator ++ new GroundTestConfig)
class DirectMemtestFPGAConfig extends Config(
new FPGAConfig ++ new DirectMemtestConfig)
class DirectComparatorFPGAConfig extends Config(
new FPGAConfig ++ new DirectComparatorConfig)