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interrupts: Crossing should use asynchronously reset registers (#1080)

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Otherwise you can get interrupts wedged high from a domain that has
not yet been clocked/powered up.
This commit is contained in:
Wesley W. Terpstra 2017-10-31 16:29:06 -07:00 committed by GitHub
parent f86489b59e
commit 8ec06151b0
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/interrupts/Crossing.scala
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@ -4,7 +4,7 @@ package freechips.rocketchip.interrupts
import Chisel._ import Chisel._
import freechips.rocketchip.config.Parameters import freechips.rocketchip.config.Parameters
import freechips.rocketchip.util.SynchronizerShiftReg import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
@ -34,7 +34,7 @@ class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Para
if (alreadyRegistered) { if (alreadyRegistered) {
out.sync := in out.sync := in
} else { } else {
out.sync := RegNext(in) out.sync := AsyncResetReg(Cat(in.reverse)).toBools
} }
} }
} }