From 8ec06151b07b1f5430917ab0968ea925dfd936a0 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 31 Oct 2017 16:29:06 -0700 Subject: [PATCH] interrupts: Crossing should use asynchronously reset registers (#1080) Otherwise you can get interrupts wedged high from a domain that has not yet been clocked/powered up. --- src/main/scala/interrupts/Crossing.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/interrupts/Crossing.scala b/src/main/scala/interrupts/Crossing.scala index d7f53a26..628dc53a 100644 --- a/src/main/scala/interrupts/Crossing.scala +++ b/src/main/scala/interrupts/Crossing.scala @@ -4,7 +4,7 @@ package freechips.rocketchip.interrupts import Chisel._ import freechips.rocketchip.config.Parameters -import freechips.rocketchip.util.SynchronizerShiftReg +import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} import freechips.rocketchip.diplomacy._ @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") @@ -34,7 +34,7 @@ class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Para if (alreadyRegistered) { out.sync := in } else { - out.sync := RegNext(in) + out.sync := AsyncResetReg(Cat(in.reverse)).toBools } } }