Merge pull request #903 from freechipsproject/monitor-probes
tilelink: use the Monitor to enforce Probe sourcing
This commit is contained in:
commit
8e2e931770
@ -19,7 +19,7 @@ case object SystemBusParams extends Field[SystemBusParams]
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class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
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class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
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private val master_splitter = LazyModule(new TLSplitter) // Allows cycle-free connection to external networks
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private val master_splitter = LazyModule(new TLSplitter) // Allows cycle-free connection to external networks
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inwardBufNode :=* master_splitter.node
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inwardNode :=* master_splitter.node
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def busView = master_splitter.node.edgesIn.head
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def busView = master_splitter.node.edgesIn.head
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protected def inwardSplitNode: TLInwardNode = master_splitter.node
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protected def inwardSplitNode: TLInwardNode = master_splitter.node
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@ -27,8 +27,10 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
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private val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
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private val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
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private val port_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
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private val port_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
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private val master_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
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master_splitter.node :=* tile_fixer.node
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master_splitter.node :=* tile_fixer.node
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master_splitter.node :=* port_fixer.node
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master_splitter.node :=* port_fixer.node
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inwardNode :=* master_fixer.node
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def toSplitSlaves: TLOutwardNode = outwardSplitNode
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def toSplitSlaves: TLOutwardNode = outwardSplitNode
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@ -36,17 +38,17 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
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val toMemoryBus: TLOutwardNode = outwardNode
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val toMemoryBus: TLOutwardNode = outwardNode
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val toSlave: TLOutwardNode = outwardNode
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val toSlave: TLOutwardNode = outwardBufNode
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def fromAsyncMasters(depth: Int = 8, sync: Int = 3): TLAsyncInwardNode = {
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def fromAsyncMasters(depth: Int = 8, sync: Int = 3): TLAsyncInwardNode = {
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val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
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val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
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inwardNode :=* sink.node
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master_fixer.node :=* sink.node
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sink.node
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sink.node
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}
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}
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def fromSyncMasters(params: BufferParams = BufferParams.default): TLInwardNode = {
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def fromSyncMasters(params: BufferParams = BufferParams.default): TLInwardNode = {
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val buffer = LazyModule(new TLBuffer(params))
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val buffer = LazyModule(new TLBuffer(params))
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inwardNode :=* buffer.node
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master_fixer.node :=* buffer.node
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buffer.node
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buffer.node
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}
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}
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@ -97,5 +97,5 @@ trait HasSystemErrorSlave extends HasSystemBus {
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private val params = p(ErrorParams)
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private val params = p(ErrorParams)
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val error = LazyModule(new TLError(params, sbus.beatBytes))
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val error = LazyModule(new TLError(params, sbus.beatBytes))
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error.node := sbus.toSlave
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error.node := TLBuffer(BufferParams.pipe)(sbus.toSlave)
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}
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}
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@ -17,8 +17,7 @@ case class RocketTileParams(
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dcache: Option[DCacheParams] = Some(DCacheParams()),
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dcache: Option[DCacheParams] = Some(DCacheParams()),
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rocc: Seq[RoCCParams] = Nil,
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rocc: Seq[RoCCParams] = Nil,
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btb: Option[BTBParams] = Some(BTBParams()),
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btb: Option[BTBParams] = Some(BTBParams()),
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dataScratchpadBytes: Int = 0,
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dataScratchpadBytes: Int = 0) extends TileParams {
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boundaryBufferParams: BufferParams = BufferParams.flow) extends TileParams {
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require(icache.isDefined)
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require(icache.isDefined)
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require(dcache.isDefined)
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require(dcache.isDefined)
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}
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}
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@ -172,11 +171,7 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
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val periphIntNode = IntInputNode()
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val periphIntNode = IntInputNode()
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val coreIntNode = IntInputNode()
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val coreIntNode = IntInputNode()
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val intXbar = LazyModule(new IntXbar)
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val intXbar = LazyModule(new IntXbar)
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val masterBuffer = LazyModule(new TLBuffer(rtp.boundaryBufferParams))
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val slaveBuffer = LazyModule(new TLBuffer(rtp.boundaryBufferParams))
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masterBuffer.node :=* rocket.masterNode
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rocket.slaveNode connectButDontMonitorSlaves slaveBuffer.node
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rocket.intNode := intXbar.intnode
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rocket.intNode := intXbar.intnode
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lazy val module = new LazyModuleImp(this) {
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lazy val module = new LazyModuleImp(this) {
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@ -195,10 +190,10 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
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class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
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class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
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val masterNode = TLOutputNode()
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val masterNode = TLOutputNode()
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masterNode :=* masterBuffer.node
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masterNode :=* rocket.masterNode
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val slaveNode = new TLInputNode() { override def reverse = true }
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val slaveNode = new TLInputNode() { override def reverse = true }
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slaveBuffer.node connectButDontMonitorSlaves slaveNode
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rocket.slaveNode connectButDontMonitorSlaves slaveNode
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// Fully async interrupts need synchronizers.
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// Fully async interrupts need synchronizers.
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// Others need no synchronization.
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// Others need no synchronization.
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@ -213,12 +208,12 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters)
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class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
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class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
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val masterNode = TLAsyncOutputNode()
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val masterNode = TLAsyncOutputNode()
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val source = LazyModule(new TLAsyncCrossingSource)
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val source = LazyModule(new TLAsyncCrossingSource)
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source.node :=* masterBuffer.node
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source.node :=* rocket.masterNode
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masterNode :=* source.node
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masterNode :=* source.node
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val slaveNode = new TLAsyncInputNode() { override def reverse = true }
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val slaveNode = new TLAsyncInputNode() { override def reverse = true }
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val sink = LazyModule(new TLAsyncCrossingSink)
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val sink = LazyModule(new TLAsyncCrossingSink)
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slaveBuffer.node connectButDontMonitorSlaves sink.node
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rocket.slaveNode connectButDontMonitorSlaves sink.node
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sink.node connectButDontMonitorSlaves slaveNode
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sink.node connectButDontMonitorSlaves slaveNode
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// Fully async interrupts need synchronizers,
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// Fully async interrupts need synchronizers,
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@ -237,12 +232,12 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters
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class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
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class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
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val masterNode = TLRationalOutputNode()
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val masterNode = TLRationalOutputNode()
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val source = LazyModule(new TLRationalCrossingSource)
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val source = LazyModule(new TLRationalCrossingSource)
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source.node :=* masterBuffer.node
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source.node :=* rocket.masterNode
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masterNode :=* source.node
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masterNode :=* source.node
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val slaveNode = new TLRationalInputNode() { override def reverse = true }
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val slaveNode = new TLRationalInputNode() { override def reverse = true }
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val sink = LazyModule(new TLRationalCrossingSink(SlowToFast))
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val sink = LazyModule(new TLRationalCrossingSink(SlowToFast))
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slaveBuffer.node connectButDontMonitorSlaves sink.node
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rocket.slaveNode connectButDontMonitorSlaves sink.node
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sink.node connectButDontMonitorSlaves slaveNode
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sink.node connectButDontMonitorSlaves slaveNode
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// Fully async interrupts need synchronizers.
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// Fully async interrupts need synchronizers.
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@ -106,10 +106,12 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
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val address_ok = edge.manager.containsSafe(edge.address(bundle))
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val address_ok = edge.manager.containsSafe(edge.address(bundle))
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val is_aligned = edge.isAligned(bundle.address, bundle.size)
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val is_aligned = edge.isAligned(bundle.address, bundle.size)
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val mask = edge.full_mask(bundle)
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val mask = edge.full_mask(bundle)
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val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => UInt(c.sourceId.start))) === bundle.source
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when (bundle.opcode === TLMessages.Probe) {
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when (bundle.opcode === TLMessages.Probe) {
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assert (edge.client.supportsProbe(bundle.source, bundle.size), "'B' channel carries Probe type unsupported by client" + extra)
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assert (edge.client.supportsProbe(bundle.source, bundle.size), "'B' channel carries Probe type unsupported by client" + extra)
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assert (address_ok, "'B' channel Probe carries unmanaged address" + extra)
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assert (address_ok, "'B' channel Probe carries unmanaged address" + extra)
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assert (legal_source, "'B' channel Probe carries source that is not first source" + extra)
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assert (is_aligned, "'B' channel Probe address not aligned to size" + extra)
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assert (is_aligned, "'B' channel Probe address not aligned to size" + extra)
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assert (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
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assert (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
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assert (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
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assert (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
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@ -118,6 +120,7 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
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when (bundle.opcode === TLMessages.Get) {
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when (bundle.opcode === TLMessages.Get) {
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assert (edge.client.supportsGet(bundle.source, bundle.size), "'B' channel carries Get type unsupported by client" + extra)
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assert (edge.client.supportsGet(bundle.source, bundle.size), "'B' channel carries Get type unsupported by client" + extra)
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assert (address_ok, "'B' channel Get carries unmanaged address" + extra)
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assert (address_ok, "'B' channel Get carries unmanaged address" + extra)
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assert (legal_source, "'B' channel Get carries source that is not first source" + extra)
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assert (is_aligned, "'B' channel Get address not aligned to size" + extra)
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assert (is_aligned, "'B' channel Get address not aligned to size" + extra)
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assert (bundle.param === UInt(0), "'B' channel Get carries invalid param" + extra)
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assert (bundle.param === UInt(0), "'B' channel Get carries invalid param" + extra)
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assert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
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assert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
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@ -126,6 +129,7 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
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when (bundle.opcode === TLMessages.PutFullData) {
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when (bundle.opcode === TLMessages.PutFullData) {
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assert (edge.client.supportsPutFull(bundle.source, bundle.size), "'B' channel carries PutFull type unsupported by client" + extra)
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assert (edge.client.supportsPutFull(bundle.source, bundle.size), "'B' channel carries PutFull type unsupported by client" + extra)
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assert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
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assert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
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assert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
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assert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
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assert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
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assert (bundle.param === UInt(0), "'B' channel PutFull carries invalid param" + extra)
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assert (bundle.param === UInt(0), "'B' channel PutFull carries invalid param" + extra)
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assert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
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assert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
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@ -134,6 +138,7 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
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when (bundle.opcode === TLMessages.PutPartialData) {
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when (bundle.opcode === TLMessages.PutPartialData) {
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assert (edge.client.supportsPutPartial(bundle.source, bundle.size), "'B' channel carries PutPartial type unsupported by client" + extra)
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assert (edge.client.supportsPutPartial(bundle.source, bundle.size), "'B' channel carries PutPartial type unsupported by client" + extra)
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assert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
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assert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
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assert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
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assert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
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assert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
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assert (bundle.param === UInt(0), "'B' channel PutPartial carries invalid param" + extra)
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assert (bundle.param === UInt(0), "'B' channel PutPartial carries invalid param" + extra)
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assert ((bundle.mask & ~mask) === UInt(0), "'B' channel PutPartial contains invalid mask" + extra)
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assert ((bundle.mask & ~mask) === UInt(0), "'B' channel PutPartial contains invalid mask" + extra)
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@ -142,6 +147,7 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
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when (bundle.opcode === TLMessages.ArithmeticData) {
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when (bundle.opcode === TLMessages.ArithmeticData) {
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assert (edge.client.supportsArithmetic(bundle.source, bundle.size), "'B' channel carries Arithmetic type unsupported by client" + extra)
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assert (edge.client.supportsArithmetic(bundle.source, bundle.size), "'B' channel carries Arithmetic type unsupported by client" + extra)
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assert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
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assert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
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assert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
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assert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
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assert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
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assert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
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assert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
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assert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
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assert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
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@ -150,6 +156,7 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
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when (bundle.opcode === TLMessages.LogicalData) {
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when (bundle.opcode === TLMessages.LogicalData) {
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assert (edge.client.supportsLogical(bundle.source, bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
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assert (edge.client.supportsLogical(bundle.source, bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
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assert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
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assert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
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assert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
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assert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
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assert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
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assert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
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assert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
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assert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
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assert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
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@ -158,6 +165,7 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
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when (bundle.opcode === TLMessages.Hint) {
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when (bundle.opcode === TLMessages.Hint) {
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assert (edge.client.supportsHint(bundle.source, bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
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assert (edge.client.supportsHint(bundle.source, bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
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assert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
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assert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
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assert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
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assert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
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assert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
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assert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
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assert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
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}
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}
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