diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala index ff0003e6..9fe8a56b 100644 --- a/src/main/scala/coreplex/SystemBus.scala +++ b/src/main/scala/coreplex/SystemBus.scala @@ -19,7 +19,7 @@ case object SystemBusParams extends Field[SystemBusParams] class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params) { private val master_splitter = LazyModule(new TLSplitter) // Allows cycle-free connection to external networks - inwardBufNode :=* master_splitter.node + inwardNode :=* master_splitter.node def busView = master_splitter.node.edgesIn.head protected def inwardSplitNode: TLInwardNode = master_splitter.node @@ -27,8 +27,10 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr private val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable)) private val port_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all)) + private val master_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all)) master_splitter.node :=* tile_fixer.node master_splitter.node :=* port_fixer.node + inwardNode :=* master_fixer.node def toSplitSlaves: TLOutwardNode = outwardSplitNode @@ -36,17 +38,17 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr val toMemoryBus: TLOutwardNode = outwardNode - val toSlave: TLOutwardNode = outwardNode + val toSlave: TLOutwardNode = outwardBufNode def fromAsyncMasters(depth: Int = 8, sync: Int = 3): TLAsyncInwardNode = { val sink = LazyModule(new TLAsyncCrossingSink(depth, sync)) - inwardNode :=* sink.node + master_fixer.node :=* sink.node sink.node } def fromSyncMasters(params: BufferParams = BufferParams.default): TLInwardNode = { val buffer = LazyModule(new TLBuffer(params)) - inwardNode :=* buffer.node + master_fixer.node :=* buffer.node buffer.node } diff --git a/src/main/scala/devices/tilelink/Error.scala b/src/main/scala/devices/tilelink/Error.scala index d054922e..bc43b4ff 100644 --- a/src/main/scala/devices/tilelink/Error.scala +++ b/src/main/scala/devices/tilelink/Error.scala @@ -97,5 +97,5 @@ trait HasSystemErrorSlave extends HasSystemBus { private val params = p(ErrorParams) val error = LazyModule(new TLError(params, sbus.beatBytes)) - error.node := sbus.toSlave + error.node := TLBuffer(BufferParams.pipe)(sbus.toSlave) } diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala index 7afcb64d..4bb6661e 100644 --- a/src/main/scala/tile/RocketTile.scala +++ b/src/main/scala/tile/RocketTile.scala @@ -17,8 +17,7 @@ case class RocketTileParams( dcache: Option[DCacheParams] = Some(DCacheParams()), rocc: Seq[RoCCParams] = Nil, btb: Option[BTBParams] = Some(BTBParams()), - dataScratchpadBytes: Int = 0, - boundaryBufferParams: BufferParams = BufferParams.flow) extends TileParams { + dataScratchpadBytes: Int = 0) extends TileParams { require(icache.isDefined) require(dcache.isDefined) } @@ -172,11 +171,7 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p: val periphIntNode = IntInputNode() val coreIntNode = IntInputNode() val intXbar = LazyModule(new IntXbar) - val masterBuffer = LazyModule(new TLBuffer(rtp.boundaryBufferParams)) - val slaveBuffer = LazyModule(new TLBuffer(rtp.boundaryBufferParams)) - masterBuffer.node :=* rocket.masterNode - rocket.slaveNode connectButDontMonitorSlaves slaveBuffer.node rocket.intNode := intXbar.intnode lazy val module = new LazyModuleImp(this) { @@ -195,10 +190,10 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p: class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) { val masterNode = TLOutputNode() - masterNode :=* masterBuffer.node + masterNode :=* rocket.masterNode val slaveNode = new TLInputNode() { override def reverse = true } - slaveBuffer.node connectButDontMonitorSlaves slaveNode + rocket.slaveNode connectButDontMonitorSlaves slaveNode // Fully async interrupts need synchronizers. // Others need no synchronization. @@ -213,12 +208,12 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) { val masterNode = TLAsyncOutputNode() val source = LazyModule(new TLAsyncCrossingSource) - source.node :=* masterBuffer.node + source.node :=* rocket.masterNode masterNode :=* source.node val slaveNode = new TLAsyncInputNode() { override def reverse = true } val sink = LazyModule(new TLAsyncCrossingSink) - slaveBuffer.node connectButDontMonitorSlaves sink.node + rocket.slaveNode connectButDontMonitorSlaves sink.node sink.node connectButDontMonitorSlaves slaveNode // Fully async interrupts need synchronizers, @@ -237,12 +232,12 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) { val masterNode = TLRationalOutputNode() val source = LazyModule(new TLRationalCrossingSource) - source.node :=* masterBuffer.node + source.node :=* rocket.masterNode masterNode :=* source.node val slaveNode = new TLRationalInputNode() { override def reverse = true } val sink = LazyModule(new TLRationalCrossingSink(SlowToFast)) - slaveBuffer.node connectButDontMonitorSlaves sink.node + rocket.slaveNode connectButDontMonitorSlaves sink.node sink.node connectButDontMonitorSlaves slaveNode // Fully async interrupts need synchronizers. diff --git a/src/main/scala/tilelink/Monitor.scala b/src/main/scala/tilelink/Monitor.scala index e88a55a6..5b06ffd5 100644 --- a/src/main/scala/tilelink/Monitor.scala +++ b/src/main/scala/tilelink/Monitor.scala @@ -106,10 +106,12 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args) val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) + val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => UInt(c.sourceId.start))) === bundle.source when (bundle.opcode === TLMessages.Probe) { assert (edge.client.supportsProbe(bundle.source, bundle.size), "'B' channel carries Probe type unsupported by client" + extra) assert (address_ok, "'B' channel Probe carries unmanaged address" + extra) + assert (legal_source, "'B' channel Probe carries source that is not first source" + extra) assert (is_aligned, "'B' channel Probe address not aligned to size" + extra) assert (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assert (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) @@ -118,6 +120,7 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args) when (bundle.opcode === TLMessages.Get) { assert (edge.client.supportsGet(bundle.source, bundle.size), "'B' channel carries Get type unsupported by client" + extra) assert (address_ok, "'B' channel Get carries unmanaged address" + extra) + assert (legal_source, "'B' channel Get carries source that is not first source" + extra) assert (is_aligned, "'B' channel Get address not aligned to size" + extra) assert (bundle.param === UInt(0), "'B' channel Get carries invalid param" + extra) assert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) @@ -126,6 +129,7 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args) when (bundle.opcode === TLMessages.PutFullData) { assert (edge.client.supportsPutFull(bundle.source, bundle.size), "'B' channel carries PutFull type unsupported by client" + extra) assert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) + assert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) assert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) assert (bundle.param === UInt(0), "'B' channel PutFull carries invalid param" + extra) assert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) @@ -134,6 +138,7 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args) when (bundle.opcode === TLMessages.PutPartialData) { assert (edge.client.supportsPutPartial(bundle.source, bundle.size), "'B' channel carries PutPartial type unsupported by client" + extra) assert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) + assert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) assert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) assert (bundle.param === UInt(0), "'B' channel PutPartial carries invalid param" + extra) assert ((bundle.mask & ~mask) === UInt(0), "'B' channel PutPartial contains invalid mask" + extra) @@ -142,6 +147,7 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args) when (bundle.opcode === TLMessages.ArithmeticData) { assert (edge.client.supportsArithmetic(bundle.source, bundle.size), "'B' channel carries Arithmetic type unsupported by client" + extra) assert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) + assert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) assert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) assert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) assert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) @@ -150,6 +156,7 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args) when (bundle.opcode === TLMessages.LogicalData) { assert (edge.client.supportsLogical(bundle.source, bundle.size), "'B' channel carries Logical type unsupported by client" + extra) assert (address_ok, "'B' channel Logical carries unmanaged address" + extra) + assert (legal_source, "'B' channel Logical carries source that is not first source" + extra) assert (is_aligned, "'B' channel Logical address not aligned to size" + extra) assert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) assert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) @@ -158,6 +165,7 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args) when (bundle.opcode === TLMessages.Hint) { assert (edge.client.supportsHint(bundle.source, bundle.size), "'B' channel carries Hint type unsupported by client" + extra) assert (address_ok, "'B' channel Hint carries unmanaged address" + extra) + assert (legal_source, "'B' channel Hint carries source that is not first source" + extra) assert (is_aligned, "'B' channel Hint address not aligned to size" + extra) assert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) }