riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Fix bug with multiple DecodeLogics per module

Browse Source
This commit is contained in:
Andrew Waterman 2014-05-04 20:02:31 -07:00
parent 5bc6981414
commit 8dcc0cbb53
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
rocket/src/main/scala/decode.scala
View File

@ -20,7 +20,7 @@ object DecodeLogic
}.foldLeft(Bool(false))(_||_) }.foldLeft(Bool(false))(_||_)
} }
def apply[T <: Bits](addr: UInt, default: T, mapping: Iterable[(UInt, T)]): T = { def apply[T <: Bits](addr: UInt, default: T, mapping: Iterable[(UInt, T)]): T = {
val cache = caches.getOrElseUpdate(Module.current, collection.mutable.Map[Term,Bool]()) val cache = caches.getOrElseUpdate(addr, collection.mutable.Map[Term,Bool]())
val dterm = term(default) val dterm = term(default)
val (keys, values) = mapping.unzip val (keys, values) = mapping.unzip
val addrWidth = keys.map(_.getWidth).max val addrWidth = keys.map(_.getWidth).max
@ -59,7 +59,7 @@ object DecodeLogic
apply(addr, Bool.DC, trues.map(_ -> Bool(true)) ++ falses.map(_ -> Bool(false))) apply(addr, Bool.DC, trues.map(_ -> Bool(true)) ++ falses.map(_ -> Bool(false)))
def apply(addr: UInt, tru: UInt, fals: UInt): Bool = def apply(addr: UInt, tru: UInt, fals: UInt): Bool =
apply(addr, Seq(tru), Seq(fals)) apply(addr, Seq(tru), Seq(fals))
private val caches = collection.mutable.Map[Module,collection.mutable.Map[Term,Bool]]() private val caches = collection.mutable.Map[UInt,collection.mutable.Map[Term,Bool]]()
} }
class Term(val value: BigInt, val mask: BigInt = 0) class Term(val value: BigInt, val mask: BigInt = 0)