riscv/rocket-chip
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try to give seqmems clearer names

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This commit is contained in:
Henry Cook
2017-09-19 13:41:11 -07:00
parent e8702e2687
commit 8db5bbbae0
4 changed files with 19 additions and 19 deletions
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12
src/main/scala/rocket/NBDcache.scala
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@ -628,12 +628,12 @@ class DataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val resp = Wire(Vec(rowWords, Bits(width = encRowBits)))
val r_raddr = RegEnable(io.read.bits.addr, io.read.valid)
for (i <- 0 until resp.size) {
val array = SeqMem(nSets*refillCycles, Vec(rowWords, Bits(width=encDataBits)))
val nbdcache_data_array = SeqMem(nSets*refillCycles, Vec(rowWords, Bits(width=encDataBits)))
when (wway_en.orR && io.write.valid && io.write.bits.wmask(i)) {
val data = Vec.fill(rowWords)(io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i))
array.write(waddr, data, wway_en.toBools)
nbdcache_data_array.write(waddr, data, wway_en.toBools)
}
resp(i) := array.read(raddr, rway_en.orR && io.read.valid).asUInt
resp(i) := nbdcache_data_array.read(raddr, rway_en.orR && io.read.valid).asUInt
}
for (dw <- 0 until rowWords) {
val r = Vec(resp.map(_(encDataBits*(dw+1)-1,encDataBits*dw)))
@ -645,12 +645,12 @@ class DataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
}
} else {
for (w <- 0 until nWays) {
val array = SeqMem(nSets*refillCycles, Vec(rowWords, Bits(width=encDataBits)))
val nbdcache_data_array = SeqMem(nSets*refillCycles, Vec(rowWords, Bits(width=encDataBits)))
when (io.write.bits.way_en(w) && io.write.valid) {
val data = Vec.tabulate(rowWords)(i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i))
array.write(waddr, data, io.write.bits.wmask.toBools)
nbdcache_data_array.write(waddr, data, io.write.bits.wmask.toBools)
}
io.resp(w) := array.read(raddr, io.read.bits.way_en(w) && io.read.valid).asUInt
io.resp(w) := nbdcache_data_array.read(raddr, io.read.bits.way_en(w) && io.read.valid).asUInt
}
}