riscv/rocket-chip
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Merge pull request #876 from freechipsproject/sq-helper

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ShiftQueue: support constant propagation
This commit is contained in:
Wesley W. Terpstra 2017-07-18 16:30:23 -07:00 committed by GitHub
commit 8d793daf9c
2 changed files with 17 additions and 5 deletions
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8
src/main/scala/diplomacy/Parameters.scala
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@ -3,6 +3,7 @@
package freechips.rocketchip.diplomacy package freechips.rocketchip.diplomacy
import Chisel._ import Chisel._
import freechips.rocketchip.util.ShiftQueue
/** Options for memory regions */ /** Options for memory regions */
object RegionType { object RegionType {
@ -267,6 +268,13 @@ case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
def apply[T <: Data](x: DecoupledIO[T]) = def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
} }
object BufferParams object BufferParams

14
src/main/scala/util/ShiftQueue.scala
View File

@ -17,8 +17,7 @@ class ShiftQueue[T <: Data](gen: T,
val mask = UInt(OUTPUT, entries) val mask = UInt(OUTPUT, entries)
}) })
private val ram = Mem(entries, gen) private val valid = RegInit(Vec.fill(entries) { Bool(false) })
private val valid = RegInit(UInt(0, entries))
private val elts = Reg(Vec(entries, gen)) private val elts = Reg(Vec(entries, gen))
private val do_enq = io.enq.fire() private val do_enq = io.enq.fire()
@ -30,7 +29,12 @@ class ShiftQueue[T <: Data](gen: T,
val enqNew = io.enq.fire() && Mux(io.deq.ready, valid(i), !valid(i) && (if (i == 0) true.B else valid(i-1))) val enqNew = io.enq.fire() && Mux(io.deq.ready, valid(i), !valid(i) && (if (i == 0) true.B else valid(i-1)))
when (shiftDown || enqNew) { elts(i) := wdata } when (shiftDown || enqNew) { elts(i) := wdata }
} }
when (do_enq =/= do_deq) { valid := Mux(do_enq, (valid << 1) | UInt(1), valid >> 1) }
val padded = Seq(true.B) ++ valid ++ Seq(false.B)
for (i <- 0 until entries) {
when ( do_enq && !do_deq && padded(i+0)) { valid(i) := true.B }
when (!do_enq && do_deq && !padded(i+2)) { valid(i) := false.B }
}
io.enq.ready := !valid(entries-1) io.enq.ready := !valid(entries-1)
io.deq.valid := valid(0) io.deq.valid := valid(0)
@ -45,6 +49,6 @@ class ShiftQueue[T <: Data](gen: T,
when (io.deq.ready) { io.enq.ready := true.B } when (io.deq.ready) { io.enq.ready := true.B }
} }
io.count := PopCount(valid) io.mask := valid.asUInt
io.mask := valid io.count := PopCount(io.mask)
} }