riscv/rocket-chip
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Bump chisel and firrtl (#1232)

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* Misc changes to better enable autoclonetype
* Bump chisel3 and firrtl and SBT to 1.1.1
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Jack Koenig authored and GitHub committed 2018-03-01 15:19:12 -08:00
1 parent 20a8876856
commit 8c6e745653
10 files changed
+10 -22
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src/main/scala/rocket/Frontend.scala
+1 -1
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@@ -62,7 +62,7 @@ class Frontend(val icacheParams: ICacheParams, hartid: Int)(implicit p: Paramete
val slaveNode = icache.slaveNode
}
class FrontendBundle(outer: Frontend) extends CoreBundle()(outer.p)
class FrontendBundle(val outer: Frontend) extends CoreBundle()(outer.p)
with HasExternallyDrivenTileConstants {
val cpu = new FrontendIO().flip
val ptw = new TLBPTWIO()