coreplex: leverage improved := composition

2017-10-25 02:27:01 -07:00
parent e894d64bca
commit 8c5e8dd071
6 changed files with 16 additions and 56 deletions
--- a/src/main/scala/groundtest/Coreplex.scala
+++ b/src/main/scala/groundtest/Coreplex.scala
@ -26,9 +26,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
  )}

  tiles.flatMap(_.dcacheOpt).foreach { dc =>
-    sbus.fromTile(
-      adapt = TileMasterPortParams(addBuffers = 1).adapt(this) _,
-      from = dc.node)
+    sbus.fromTile(None) { implicit p => TileMasterPortParams(addBuffers = 1).adapt(this)(dc.node) }
  }

  val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), true, false, pbus.beatBytes))