From 8c5e8dd0712f891e77148c7267f6205cbb3eca83 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 25 Oct 2017 02:27:01 -0700 Subject: [PATCH] coreplex: leverage improved := composition --- src/main/scala/coreplex/CrossingWrapper.scala | 4 +- src/main/scala/coreplex/PeripheryBus.scala | 7 +--- src/main/scala/coreplex/RocketCoreplex.scala | 39 +++++-------------- src/main/scala/coreplex/SystemBus.scala | 7 +--- src/main/scala/groundtest/Coreplex.scala | 4 +- src/main/scala/tilelink/Buffer.scala | 11 +----- 6 files changed, 16 insertions(+), 56 deletions(-) diff --git a/src/main/scala/coreplex/CrossingWrapper.scala b/src/main/scala/coreplex/CrossingWrapper.scala index 6a7b3a93..e0b888be 100644 --- a/src/main/scala/coreplex/CrossingWrapper.scala +++ b/src/main/scala/coreplex/CrossingWrapper.scala @@ -24,9 +24,7 @@ trait HasCrossingHelper extends LazyScope val out = x.node.parentsOut.exists(_ eq this) // is the crossing exiting the wrapper? crossing match { case SynchronousCrossing(params) => { - // !!! Why does star resolution fail for tile with no slave devices? - // this { TLBuffer(params)(x.node) } - x.node + this { TLBuffer(params)(x.node) } } case RationalCrossing(direction) => { def sourceGen = LazyModule(new TLRationalCrossingSource) diff --git a/src/main/scala/coreplex/PeripheryBus.scala b/src/main/scala/coreplex/PeripheryBus.scala index c3a6939d..49f0b25b 100644 --- a/src/main/scala/coreplex/PeripheryBus.scala +++ b/src/main/scala/coreplex/PeripheryBus.scala @@ -37,15 +37,12 @@ class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends T atomics.node } - def toTile( - adapt: TLOutwardNode => TLOutwardNode, - to: TLInwardNode, - name: Option[String] = None) { + def toTile(name: Option[String] = None)(gen: Parameters => TLInwardNode) { this { LazyScope(s"${busName}ToTile${name.getOrElse("")}") { SinkCardinality { implicit p => FlipRendering { implicit p => - to :*= adapt(outwardNode) + gen(p) :*= outwardNode } } } diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala index d3f5859d..943edc73 100644 --- a/src/main/scala/coreplex/RocketCoreplex.scala +++ b/src/main/scala/coreplex/RocketCoreplex.scala @@ -28,18 +28,11 @@ case class TileMasterPortParams( .map(BasicBusBlockerParams(_, coreplex.pbus.beatBytes, coreplex.sbus.beatBytes, deadlock = true)) .map(bp => LazyModule(new BasicBusBlocker(bp))) val tile_master_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable)) - val tile_master_buffer = LazyModule(new TLBufferChain(addBuffers)) - - val node: Option[TLNode] = TLNodeChain(List( - Some(tile_master_buffer.node), - Some(tile_master_fixer.node), - tile_master_blocker.map(_.node), - tile_master_cork.map(_.node)).flatten) tile_master_blocker.foreach { _.controlNode := coreplex.pbus.toVariableWidthSlaves } - node.foreach { _ :=* masterNode } - - node.getOrElse(masterNode) + (Seq(tile_master_fixer.node) ++ TLBuffer.chain(addBuffers) + ++ tile_master_blocker.map(_.node) ++ tile_master_cork.map(_.node)) + .foldRight(masterNode)(_ :=* _) } } @@ -48,22 +41,16 @@ case class TileSlavePortParams( blockerCtrlAddr: Option[BigInt] = None) { def adapt(coreplex: HasPeripheryBus) - (masterNode: TLOutwardNode) - (implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = { + (slaveNode: TLInwardNode) + (implicit p: Parameters, sourceInfo: SourceInfo): TLInwardNode = { val tile_slave_blocker = blockerCtrlAddr .map(BasicBusBlockerParams(_, coreplex.pbus.beatBytes, coreplex.sbus.beatBytes)) .map(bp => LazyModule(new BasicBusBlocker(bp))) - val tile_slave_buffer = LazyModule(new TLBufferChain(addBuffers)) - - val node: Option[TLNode] = TLNodeChain(List( - Some(tile_slave_buffer.node), - tile_slave_blocker.map(_.node)).flatten) tile_slave_blocker.foreach { _.controlNode := coreplex.pbus.toVariableWidthSlaves } - node.foreach { _ :*= masterNode } - - node.getOrElse(masterNode) + (TLBuffer.chain(addBuffers) ++ tile_slave_blocker.map(_.node)) + .foldLeft(slaveNode)(_ :*= _) } } @@ -116,18 +103,10 @@ trait HasRocketTiles extends HasTiles ).suggestName(tp.name) // Connect the master ports of the tile to the system bus - sbus.fromTile( - adapt = {x: TLOutwardNode => wrapper.cross(x) } andThen - crossing.master.adapt(this) _, - from = wrapper.masterNode, - name = tp.name) + sbus.fromTile(tp.name) { implicit p => crossing.master.adapt(this)(wrapper.cross(wrapper.masterNode)) } // Connect the slave ports of the tile to the periphery bus - pbus.toTile( - adapt = {x: TLOutwardNode => wrapper.cross(x) } compose - crossing.slave.adapt(this) _, - to = wrapper.slaveNode, - name = tp.name) + pbus.toTile(tp.name) { implicit p => crossing.slave.adapt(this)(wrapper.slaveNode) } // !!! wrapper.cross // Handle all the different types of interrupts crossing to or from the tile: // 1. Debug interrupt is definitely asynchronous in all cases. diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala index a87726a6..46820c76 100644 --- a/src/main/scala/coreplex/SystemBus.scala +++ b/src/main/scala/coreplex/SystemBus.scala @@ -52,14 +52,11 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr def fromFrontBus: TLInwardNode = master_splitter.node - def fromTile( - adapt: TLOutwardNode => TLOutwardNode, - from: TLOutwardNode, - name: Option[String] = None) { + def fromTile(name: Option[String])(gen: Parameters => TLOutwardNode) { this { LazyScope(s"${busName}FromTile${name.getOrElse("")}") { SourceCardinality { implicit p => - master_splitter.node :=* adapt(from) + master_splitter.node :=* gen(p) } } } diff --git a/src/main/scala/groundtest/Coreplex.scala b/src/main/scala/groundtest/Coreplex.scala index d8eff447..73a37433 100644 --- a/src/main/scala/groundtest/Coreplex.scala +++ b/src/main/scala/groundtest/Coreplex.scala @@ -26,9 +26,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex )} tiles.flatMap(_.dcacheOpt).foreach { dc => - sbus.fromTile( - adapt = TileMasterPortParams(addBuffers = 1).adapt(this) _, - from = dc.node) + sbus.fromTile(None) { implicit p => TileMasterPortParams(addBuffers = 1).adapt(this)(dc.node) } } val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), true, false, pbus.beatBytes)) diff --git a/src/main/scala/tilelink/Buffer.scala b/src/main/scala/tilelink/Buffer.scala index ba7006e2..6026bde1 100644 --- a/src/main/scala/tilelink/Buffer.scala +++ b/src/main/scala/tilelink/Buffer.scala @@ -79,18 +79,9 @@ object TLBuffer } } -object TLNodeChain { - def apply(nodes: Seq[TLNode])(implicit p: Parameters): Option[TLNode] = if(nodes.size > 0) { - (nodes.init zip nodes.tail) foreach { case (prev, next) => next :=? prev } - Some(NodeHandle(nodes.head, nodes.last)) - } else { - None - } -} - class TLBufferChain(depth: Int)(implicit p: Parameters) extends SimpleLazyModule { val buf_chain = List.fill(depth)(LazyModule(new TLBuffer(BufferParams.default))) - val node = TLNodeChain(buf_chain.map(_.node)).getOrElse(TLIdentityNode()) + val node = buf_chain.map(_.node:TLNode).reduceOption(_ :=? _).getOrElse(TLIdentityNode()) } object TLBufferChain