riscv/rocket-chip
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drop vec_irq_aux pcr register, now everything goes through badvaddr

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This commit is contained in:
Yunsup Lee 2012-03-17 14:03:57 -07:00
parent 3b4680a834
commit 8c50c81b81
2 changed files with 1 additions and 5 deletions
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1
rocket/src/main/scala/consts.scala
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@ -143,7 +143,6 @@ object Constants
val PCR_FROMHOST = UFix(17, 5);
val PCR_VECBANK = UFix(18, 5);
val PCR_VECCFG = UFix(19, 5);
val PCR_VECIRQAUX= UFix(20, 5)
// definition of bits in PCR status reg
val SR_ET = 0; // enable traps

5
rocket/src/main/scala/dpath_util.scala
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@ -102,7 +102,6 @@ class rocketDpathPCR extends Component
val reg_k1 = Reg() { Bits() };
val reg_ptbr = Reg() { UFix() };
val reg_vecbank = Reg(resetVal = Bits("b1111_1111", 8))
val reg_vec_irq_aux = Reg() { Bits() }
val reg_error_mode = Reg(resetVal = Bool(false));
val reg_status_vm = Reg(resetVal = Bool(false));
@ -149,7 +148,7 @@ class rocketDpathPCR extends Component
reg_badvaddr := Cat(badvaddr_sign, io.w.data(VADDR_BITS-1,0)).toUFix;
}
when (io.vec_irq_aux_wen) {
reg_vec_irq_aux := io.vec_irq_aux
reg_badvaddr := io.vec_irq_aux.toUFix
}
when (io.exception) {
@ -213,7 +212,6 @@ class rocketDpathPCR extends Component
when (waddr === PCR_K1) { reg_k1 := wdata; }
when (waddr === PCR_PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
when (waddr === PCR_VECBANK) { reg_vecbank := wdata(7,0) }
when (waddr === PCR_VECIRQAUX) { reg_vec_irq_aux := wdata }
}
rdata := Bits(0, 64)
@ -234,7 +232,6 @@ class rocketDpathPCR extends Component
is (PCR_PTBR) { rdata := Cat(Bits(0,64-PADDR_BITS), reg_ptbr); }
is (PCR_VECBANK) { rdata := Cat(Bits(0, 56), reg_vecbank) }
is (PCR_VECCFG) { rdata := Cat(Bits(0, 40), io.vec_nfregs, io.vec_nxregs, io.vec_appvl) }
is (PCR_VECIRQAUX){ rdata := reg_vec_irq_aux }
}
}
}