riscv/rocket-chip
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drop vec_irq_aux pcr register, now everything goes through badvaddr

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Yunsup Lee committed 2012-03-17 14:03:57 -07:00
1 parent 3b4680a834
commit 8c50c81b81
2 files changed
+1 -5
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rocket/src/main/scala/consts.scala
-1
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@@ -143,7 +143,6 @@ object Constants
val PCR_FROMHOST = UFix(17, 5);
val PCR_VECBANK = UFix(18, 5);
val PCR_VECCFG = UFix(19, 5);
val PCR_VECIRQAUX= UFix(20, 5)
// definition of bits in PCR status reg
val SR_ET = 0; // enable traps