drop vec_irq_aux pcr register, now everything goes through badvaddr

2012-03-17 14:03:57 -07:00
parent 3b4680a834
commit 8c50c81b81
2 changed files with 1 additions and 5 deletions
--- a/rocket/src/main/scala/consts.scala
+++ b/rocket/src/main/scala/consts.scala
@ -143,7 +143,6 @@ object Constants
  val PCR_FROMHOST = UFix(17, 5);
  val PCR_VECBANK  = UFix(18, 5);
  val PCR_VECCFG   = UFix(19, 5);
-  val PCR_VECIRQAUX= UFix(20, 5)

  // definition of bits in PCR status reg
  val SR_ET   = 0;  // enable traps