riscv/rocket-chip
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add buffering and locking to TL -> AXI converter

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This commit is contained in:
Howard Mao
2016-07-06 16:54:58 -07:00
parent e27cb5f885
commit 8c13e78ab5
4 changed files with 5 additions and 3 deletions
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2
groundtest

Submodule groundtest updated: 4ecc9ec310...a7c8c20300

2
junctions

Submodule junctions updated: 4c04c27df8...46db745fe3

2
src/main/scala/Configs.scala
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@@ -8,6 +8,7 @@ import uncore.tilelink._
import uncore.coherence._ import uncore.coherence._
import uncore.agents._ import uncore.agents._
import uncore.devices._ import uncore.devices._
import uncore.converters._
import rocket._ import rocket._
import rocket.Util._ import rocket.Util._
import groundtest._ import groundtest._
@@ -307,6 +308,7 @@ class BaseConfig extends Config (
case ConfigString => makeConfigString() case ConfigString => makeConfigString()
case GlobalAddrMap => globalAddrMap case GlobalAddrMap => globalAddrMap
case EnableL2Logging => false case EnableL2Logging => false
case NastiResponseBufferDepth => site(MIFDataBeats) * site(NAcquireTransactors)
case _ => throw new CDEMatchError case _ => throw new CDEMatchError
}}, }},
knobValues = { knobValues = {

2
uncore

Submodule uncore updated: 8d28d89b18...2109a48e18