riscv/rocket-chip
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ext: support multiple external AHB/AXI ports

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This commit is contained in:
Wesley W. Terpstra 2016-07-05 12:40:14 -07:00
parent 36720d915a
commit 8ac7fa5544
2 changed files with 33 additions and 52 deletions
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27
src/main/scala/Configs.scala
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@ -38,25 +38,10 @@ class BaseConfig extends Config (
} }
lazy val globalAddrMap = { lazy val globalAddrMap = {
val memBase = 0x80000000L val memBase = 0x80000000L
val memSize = 0x80000000L val memSize = 0x10000000L
val io = AddrMap((AddrMapEntry("int", internalIOAddrMap) +: site(ExtMMIOPorts).entries):_*)
val ioMap = ListBuffer(AddrMapEntry("int", internalIOAddrMap))
val nMMIOChannels =
site(NExtMMIOAXIChannels) +
site(NExtMMIOAHBChannels) +
site(NExtMMIOTLChannels)
if (nMMIOChannels > 0) {
val extIOBase = 0x60000000L
val extIOSize = 0x20000000L
ioMap += AddrMapEntry("ext", MemRange(extIOBase, extIOSize, MemAttr(AddrMapProt.RWX)))
Dump("IO_BASE", extIOBase)
Dump("IO_SIZE", extIOSize)
}
val addrMap = AddrMap( val addrMap = AddrMap(
AddrMapEntry("io", new AddrMap(ioMap.toSeq)), AddrMapEntry("io", io),
AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true)))) AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true))))
Dump("MEM_BASE", addrMap("mem").start) Dump("MEM_BASE", addrMap("mem").start)
@ -231,6 +216,12 @@ class BaseConfig extends Config (
true true
} }
case NExtInterrupts => 2 case NExtInterrupts => 2
case ExtMMIOPorts => AddrMap()
/*
AddrMap(
AddrMapEntry("cfg", MemRange(0x50000000L, 0x04000000L, MemAttr(AddrMapProt.RW))),
AddrMapEntry("ext", MemRange(0x60000000L, 0x20000000L, MemAttr(AddrMapProt.RWX))))
*/
case NExtMMIOAXIChannels => 0 case NExtMMIOAXIChannels => 0
case NExtMMIOAHBChannels => 0 case NExtMMIOAHBChannels => 0
case NExtMMIOTLChannels => 0 case NExtMMIOTLChannels => 0

54
src/main/scala/RocketChip.scala
View File

@ -35,6 +35,7 @@ case object BankIdLSB extends Field[Int]
/** Number of outstanding memory requests */ /** Number of outstanding memory requests */
case object NOutstandingMemReqsPerChannel extends Field[Int] case object NOutstandingMemReqsPerChannel extends Field[Int]
/** Number of exteral MMIO ports */ /** Number of exteral MMIO ports */
case object ExtMMIOPorts extends Field[AddrMap]
case object NExtMMIOAXIChannels extends Field[Int] case object NExtMMIOAXIChannels extends Field[Int]
case object NExtMMIOAHBChannels extends Field[Int] case object NExtMMIOAHBChannels extends Field[Int]
case object NExtMMIOTLChannels extends Field[Int] case object NExtMMIOTLChannels extends Field[Int]
@ -226,24 +227,27 @@ class Uncore(implicit val p: Parameters) extends Module
io.mem_ahb <> outmemsys.io.mem_ahb io.mem_ahb <> outmemsys.io.mem_ahb
io.mem_tl <> outmemsys.io.mem_tl io.mem_tl <> outmemsys.io.mem_tl
def connectExternalMMIO(ext: ClientUncachedTileLinkIO)(implicit p: Parameters) { def connectExternalMMIO(ports: Seq[ClientUncachedTileLinkIO])(implicit p: Parameters) {
val mmio_axi = p(NExtMMIOAXIChannels) val mmio_axi_start = 0
val mmio_ahb = p(NExtMMIOAHBChannels) val mmio_axi_end = mmio_axi_start + p(NExtMMIOAXIChannels)
val mmio_tl = p(NExtMMIOTLChannels) val mmio_ahb_start = mmio_axi_end
val mmio_ahb_end = mmio_ahb_start + p(NExtMMIOAHBChannels)
val mmio_tl_start = mmio_ahb_end
val mmio_tl_end = mmio_tl_start + p(NExtMMIOTLChannels)
require (mmio_tl_end == ports.size)
require (mmio_axi + mmio_ahb + mmio_tl <= 1) for (i <- 0 until ports.size) {
if (mmio_ahb == 1) { if (mmio_axi_start <= i && i < mmio_axi_end) {
val ahb = Module(new AHBBridge(true)) // with atomics TopUtils.connectTilelinkNasti(io.mmio_axi(i-mmio_axi_start), ports(i))
io.mmio_ahb.head <> ahb.io.ahb } else if (mmio_ahb_start <= i && i < mmio_ahb_end) {
ahb.io.tl <> ext val ahbBridge = Module(new AHBBridge(true))
} else if (mmio_tl == 1) { io.mmio_ahb(i-mmio_ahb_start) <> ahbBridge.io.ahb
TopUtils.connectTilelink(io.mmio_tl.head, ext) ahbBridge.io.tl <> ports(i)
} else if (mmio_tl_start <= i && i < mmio_tl_end) {
TopUtils.connectTilelink(io.mmio_tl(i-mmio_tl_start), ports(i))
} else { } else {
val mmioEndpoint = mmio_axi match { TopUtils.connectTilelinkNasti(Module(new NastiErrorSlave).io, ports(i))
case 0 => Module(new NastiErrorSlave).io
case 1 => io.mmio_axi.head
} }
TopUtils.connectTilelinkNasti(mmioEndpoint, ext)
} }
} }
@ -282,23 +286,9 @@ class Uncore(implicit val p: Parameters) extends Module
val bootROM = Module(new ROMSlave(TopUtils.makeBootROM())) val bootROM = Module(new ROMSlave(TopUtils.makeBootROM()))
bootROM.io <> mmioNetwork.port("int:bootrom") bootROM.io <> mmioNetwork.port("int:bootrom")
require(io.mmio_ahb.size + io.mmio_axi.size + io.mmio_tl.size <= 1, // The memory map presently has only one external I/O region
"Maximum of 1 external MMIO channel supported for now") val ext = p(ExtMMIOPorts).entries.map(port => TileLinkWidthAdapter(mmioNetwork.port(port.name), "MMIO_Outermost"))
connectExternalMMIO(ext)(outermostMMIOParams)
io.mmio_ahb.foreach { ahb =>
val ext = TileLinkWidthAdapter(mmioNetwork.port("ext"), "MMIO_Outermost")
TopUtils.connectTilelinkAhb(ahb, ext)(outermostMMIOParams)
}
io.mmio_axi.foreach { axi =>
val ext = TileLinkWidthAdapter(mmioNetwork.port("ext"), "MMIO_Outermost")
TopUtils.connectTilelinkNasti(axi, ext)(outermostMMIOParams)
}
io.mmio_tl.foreach { tl =>
val ext = TileLinkWidthAdapter(mmioNetwork.port("ext"), "MMIO_Outermost")
TopUtils.connectTilelink(tl, ext)(outermostMMIOParams)
}
} }
} }