riscv/rocket-chip
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ext: support multiple external AHB/AXI ports

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This commit is contained in:
Wesley W. Terpstra
2016-07-05 12:40:14 -07:00
parent 36720d915a
commit 8ac7fa5544
2 changed files with 33 additions and 52 deletions
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27
src/main/scala/Configs.scala
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@ -38,25 +38,10 @@ class BaseConfig extends Config (
}
lazy val globalAddrMap = {
val memBase = 0x80000000L
val memSize = 0x80000000L
val ioMap = ListBuffer(AddrMapEntry("int", internalIOAddrMap))
val nMMIOChannels =
site(NExtMMIOAXIChannels) +
site(NExtMMIOAHBChannels) +
site(NExtMMIOTLChannels)
if (nMMIOChannels > 0) {
val extIOBase = 0x60000000L
val extIOSize = 0x20000000L
ioMap += AddrMapEntry("ext", MemRange(extIOBase, extIOSize, MemAttr(AddrMapProt.RWX)))
Dump("IO_BASE", extIOBase)
Dump("IO_SIZE", extIOSize)
}
val memSize = 0x10000000L
val io = AddrMap((AddrMapEntry("int", internalIOAddrMap) +: site(ExtMMIOPorts).entries):_*)
val addrMap = AddrMap(
AddrMapEntry("io", new AddrMap(ioMap.toSeq)),
AddrMapEntry("io", io),
AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true))))
Dump("MEM_BASE", addrMap("mem").start)
@ -231,6 +216,12 @@ class BaseConfig extends Config (
true
}
case NExtInterrupts => 2
case ExtMMIOPorts => AddrMap()
/*
AddrMap(
AddrMapEntry("cfg", MemRange(0x50000000L, 0x04000000L, MemAttr(AddrMapProt.RW))),
AddrMapEntry("ext", MemRange(0x60000000L, 0x20000000L, MemAttr(AddrMapProt.RWX))))
*/
case NExtMMIOAXIChannels => 0
case NExtMMIOAHBChannels => 0
case NExtMMIOTLChannels => 0