riscv/rocket-chip
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changes to xcpt handling

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This commit is contained in:
Yunsup Lee 2012-03-17 17:50:37 -07:00
parent 8c50c81b81
commit 8a4f95e617
2 changed files with 3 additions and 1 deletions
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2
rocket/src/main/scala/cpu.scala
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@ -170,7 +170,7 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
vu.io.vec_ximm2q.valid := ctrl.io.vec_iface.vximm2q_valid vu.io.vec_ximm2q.valid := ctrl.io.vec_iface.vximm2q_valid
vu.io.vec_ximm2q.bits := dpath.io.vec_iface.vximm2q_bits vu.io.vec_ximm2q.bits := dpath.io.vec_iface.vximm2q_bits
vu.io.vec_cntq.valid := ctrl.io.vec_iface.vcntq_valid vu.io.vec_cntq.valid := ctrl.io.vec_iface.vcntq_valid
vu.io.vec_cntq.bits := dpath.io.vec_iface.vcntq_bits vu.io.vec_cntq.bits := Cat(dpath.io.vec_iface.vcntq_last, dpath.io.vec_iface.vcntq_bits)
// prefetch queues // prefetch queues
vu.io.vec_pfcmdq.valid := ctrl.io.vec_iface.vpfcmdq_valid vu.io.vec_pfcmdq.valid := ctrl.io.vec_iface.vpfcmdq_valid

2
rocket/src/main/scala/dpath_vec.scala
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@ -12,6 +12,7 @@ class ioDpathVecInterface extends Bundle
val vximm1q_bits = Bits(SZ_VIMM, OUTPUT) val vximm1q_bits = Bits(SZ_VIMM, OUTPUT)
val vximm2q_bits = Bits(SZ_VSTRIDE, OUTPUT) val vximm2q_bits = Bits(SZ_VSTRIDE, OUTPUT)
val vcntq_bits = Bits(SZ_VLEN, OUTPUT) val vcntq_bits = Bits(SZ_VLEN, OUTPUT)
val vcntq_last = Bool(OUTPUT)
val evac_addr = Bits(64, OUTPUT) val evac_addr = Bits(64, OUTPUT)
val irq_aux = Bits(64, INPUT) val irq_aux = Bits(64, INPUT)
} }
@ -159,6 +160,7 @@ class rocketDpathVec extends Component
io.wdata) // VIMM2_ALU io.wdata) // VIMM2_ALU
io.iface.vcntq_bits := io.wdata(SZ_VLEN-1, 0) io.iface.vcntq_bits := io.wdata(SZ_VLEN-1, 0)
io.iface.vcntq_last := io.rs2(1)
io.iface.evac_addr := io.wdata io.iface.evac_addr := io.wdata