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Merge pull request #1066 from freechipsproject/diplomacy_paper

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Add link to Diplomatic Design Patterns Paper
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Megan Wachs 2017-10-23 16:52:01 -07:00 committed by GitHub
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@ -167,7 +167,7 @@ clock-crossers and converters from TileLink to external bus protocols (e.g. AXI
This RTL package contains implementations for peripheral devices, including the Debug module and various TL slaves. This RTL package contains implementations for peripheral devices, including the Debug module and various TL slaves.
* **diplomacy** * **diplomacy**
This utility package extends Chisel by allowing for two-phase hardware elaboration, in which certain parameters This utility package extends Chisel by allowing for two-phase hardware elaboration, in which certain parameters
are dynamically negotiated between modules. are dynamically negotiated between modules. For more information about diplomacy, see [this paper](https://carrv.github.io/papers/cook-diplomacy-carrv2017.pdf).
* **groundtest** * **groundtest**
This RTL package generates synthesizeable hardware testers that emit randomized This RTL package generates synthesizeable hardware testers that emit randomized
memory access streams in order to stress-tests the uncore memory hierarchy. memory access streams in order to stress-tests the uncore memory hierarchy.