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Update Debug Module registers (#1296)

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* Debug: update versions of the files generated from the spec, mostly to get new SBA registers

* Debug: Clean up Halt Summary to use new terminology

* Debug: correct the address of HALTSUM1

* Debug: use simpler expression for numHaltedStatus

* Debug: remove now defunct haltStatus addr
This commit is contained in:
Megan Wachs
2018-03-20 14:01:22 -07:00
committed by GitHub
parent 2489a08328
commit 894960678c
3 changed files with 246 additions and 159 deletions
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3
src/main/scala/devices/debug/abstract_commands.scala
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@ -25,6 +25,9 @@ class ACCESS_REGISTERFields extends Bundle {
If \Fsize specifies a size larger than the register's actual size,
then the access must fail. If a register is accessible, then reads of \Fsize
less than or equal to the register's actual size must be supported.
This field controls the Argument Width as referenced in
Table~\ref{tab:datareg}.
*/
val size = UInt(3.W)