78 lines
2.0 KiB
Scala
78 lines
2.0 KiB
Scala
package freechips.rocketchip.devices.debug
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import Chisel._
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// This file was auto-generated from the repository at https://github.com/riscv/riscv-debug-spec.git,
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// 'make chisel'
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object AC_RegAddrs {
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}
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class ACCESS_REGISTERFields extends Bundle {
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/* This is 0 to indicate Access Register Command.
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*/
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val cmdtype = UInt(8.W)
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val reserved0 = UInt(1.W)
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/* 2: Access the lowest 32 bits of the register.
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3: Access the lowest 64 bits of the register.
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4: Access the lowest 128 bits of the register.
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If \Fsize specifies a size larger than the register's actual size,
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then the access must fail. If a register is accessible, then reads of \Fsize
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less than or equal to the register's actual size must be supported.
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This field controls the Argument Width as referenced in
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Table~\ref{tab:datareg}.
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*/
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val size = UInt(3.W)
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val reserved1 = UInt(1.W)
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/* When 1, execute the program in the Program Buffer exactly once
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after performing the transfer, if any.
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*/
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val postexec = Bool()
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/* 0: Don't do the operation specified by \Fwrite.
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1: Do the operation specified by \Fwrite.
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This bit can be used to just execute the Program Buffer without
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having to worry about placing valid values into \Fsize or \Fregno.
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*/
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val transfer = Bool()
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/* When \Ftransfer is set:
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0: Copy data from the specified register into {\tt arg0} portion
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of {\tt data}.
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1: Copy data from {\tt arg0} portion of {\tt data} into the
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specified register.
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*/
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val write = Bool()
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/* Number of the register to access, as described in
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Table~\ref{tab:regno}.
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\Rdpc may be used as an alias for PC if this command is
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supported on a non-halted hart.
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*/
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val regno = UInt(16.W)
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}
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class QUICK_ACCESSFields extends Bundle {
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/* This is 1 to indicate Quick Access command.
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*/
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val cmdtype = UInt(8.W)
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val reserved0 = UInt(24.W)
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}
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