riscv/rocket-chip
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Export stats pcr register (#28 currently) to the top-level

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This commit is contained in:
Stephen Twigg 2013-09-25 01:16:32 -07:00
parent 730a6ec76b
commit 891e459625
2 changed files with 9 additions and 2 deletions
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4
rocket/src/main/scala/dpath_util.scala
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@ -133,7 +133,6 @@ class PCR(implicit conf: RocketConfiguration) extends Module
val irq_timer = Bool(OUTPUT)
val irq_ipi = Bool(OUTPUT)
val replay = Bool(OUTPUT)
val stats = Bool(OUTPUT)
}
import PCR._
@ -172,6 +171,8 @@ class PCR(implicit conf: RocketConfiguration) extends Module
}
when (io.host.pcr_rep.fire()) { host_pcr_rep_valid := false }
io.host.debug_stats_pcr := reg_stats // direct export up the hierarchy
val addr = Mux(io.rw.cmd != PCR.N, io.rw.addr, host_pcr_bits.addr)
val wen = io.rw.cmd === PCR.T || io.rw.cmd === PCR.S || io.rw.cmd === PCR.C ||
host_pcr_req_fire && host_pcr_bits.rw
@ -183,7 +184,6 @@ class PCR(implicit conf: RocketConfiguration) extends Module
io.fatc := wen && addr === FATC
io.evec := Mux(io.exception, reg_evec.toSInt, reg_epc).toUInt
io.ptbr := reg_ptbr
io.stats := reg_stats
when (io.badvaddr_wen) {
val wdata = io.rw.wdata

7
rocket/src/main/scala/htif.scala
View File

@ -11,6 +11,7 @@ class HostIO(val w: Int) extends Bundle
val clk_edge = Bool(OUTPUT)
val in = Decoupled(Bits(width = w)).flip
val out = Decoupled(Bits(width = w))
val debug_stats_pcr = Bool(OUTPUT)
}
class PCRReq extends Bundle
@ -28,6 +29,9 @@ class HTIFIO(ntiles: Int) extends Bundle
val pcr_rep = Decoupled(Bits(width = 64))
val ipi_req = Decoupled(Bits(width = log2Up(ntiles)))
val ipi_rep = Decoupled(Bool()).flip
val debug_stats_pcr = Bool(OUTPUT)
// wired directly to stats register
// expected to be used to quickly indicate to testbench to do logging b/c in 'interesting' work
}
class SCRIO(n: Int) extends Bundle
@ -49,6 +53,9 @@ class RocketHTIF(w: Int, nSCR: Int)(implicit conf: TileLinkConfiguration) extend
val scr = new SCRIO(nSCR)
}
io.host.debug_stats_pcr := io.cpu.map(_.debug_stats_pcr).reduce(_||_)
// system is 'interesting' if any tile is 'interesting'
val short_request_bits = 64
val long_request_bits = 576
require(short_request_bits % w == 0)