Merge pull request #367 from ucb-bar/tl2-isolation

Tl2 isolation

src/main/scala/uncore/tilelink2/AtomicAutomata.scala

@@ -277,7 +277,7 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc
 object TLAtomicAutomata
 {
   // applied to the TL source node; y.node := TLAtomicAutomata(x.node)
-  def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(x: TLBaseNode)(implicit sourceInfo: SourceInfo): TLBaseNode = {
+  def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
     val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough))
     atomics.node := x
     atomics.node

src/main/scala/uncore/tilelink2/Buffer.scala

@@ -48,12 +48,12 @@ class TLBuffer(a: Int = 2, b: Int = 2, c: Int = 2, d: Int = 2, e: Int = 2, pipe:
 object TLBuffer
 {
   // applied to the TL source node; y.node := TLBuffer(x.node)
-  def apply()                                (x: TLBaseNode)(implicit sourceInfo: SourceInfo): TLBaseNode = apply(2)(x)
+  def apply()                                (x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = apply(2)(x)
-  def apply(entries: Int)                    (x: TLBaseNode)(implicit sourceInfo: SourceInfo): TLBaseNode = apply(entries, true)(x)
+  def apply(entries: Int)                    (x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = apply(entries, true)(x)
-  def apply(entries: Int, pipe: Boolean)     (x: TLBaseNode)(implicit sourceInfo: SourceInfo): TLBaseNode = apply(entries, entries, pipe)(x)
+  def apply(entries: Int, pipe: Boolean)     (x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = apply(entries, entries, pipe)(x)
-  def apply(ace: Int, bd: Int)               (x: TLBaseNode)(implicit sourceInfo: SourceInfo): TLBaseNode = apply(ace, bd, true)(x)
+  def apply(ace: Int, bd: Int)               (x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, true)(x)
-  def apply(ace: Int, bd: Int, pipe: Boolean)(x: TLBaseNode)(implicit sourceInfo: SourceInfo): TLBaseNode = apply(ace, bd, ace, bd, ace, pipe)(x)
+  def apply(ace: Int, bd: Int, pipe: Boolean)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, ace, bd, ace, pipe)(x)
-  def apply(a: Int, b: Int, c: Int, d: Int, e: Int, pipe: Boolean = true)(x: TLBaseNode)(implicit sourceInfo: SourceInfo): TLBaseNode = {
+  def apply(a: Int, b: Int, c: Int, d: Int, e: Int, pipe: Boolean = true)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
     val buffer = LazyModule(new TLBuffer(a, b, c, d, e, pipe))
     buffer.node := x
     buffer.node

src/main/scala/uncore/tilelink2/Crossing.scala

@@ -71,6 +71,26 @@ class TLAsyncCrossingSink(depth: Int = 8, sync: Int = 3) extends LazyModule
   }
 }
 
+object TLAsyncCrossingSource
+{
+  // applied to the TL source node; y.node := TLAsyncCrossingSource()(x.node)
+  def apply(sync: Int = 3)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLAsyncOutwardNode = {
+    val source = LazyModule(new TLAsyncCrossingSource(sync))
+    source.node := x
+    source.node
+  }
+}
+
+object TLAsyncCrossingSink
+{
+  // applied to the TL source node; y.node := TLAsyncCrossingSink()(x.node)
+  def apply(depth: Int = 8, sync: Int = 3)(x: TLAsyncOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
+    val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
+    sink.node := x
+    sink.node
+  }
+}
+
 class TLAsyncCrossing(depth: Int = 8, sync: Int = 3) extends LazyModule
 {
   val nodeIn = TLInputNode()

src/main/scala/uncore/tilelink2/Fragmenter.scala

@@ -244,7 +244,7 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
 object TLFragmenter
 {
   // applied to the TL source node; y.node := TLFragmenter(x.node, 256, 4)
-  def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false)(x: TLBaseNode)(implicit sourceInfo: SourceInfo): TLBaseNode = {
+  def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
     val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin))
     fragmenter.node := x
     fragmenter.node

src/main/scala/uncore/tilelink2/HintHandler.scala

@@ -135,7 +135,7 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
 object TLHintHandler
 {
   // applied to the TL source node; y.node := TLHintHandler(x.node)
-  def apply(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(x: TLBaseNode)(implicit sourceInfo: SourceInfo): TLBaseNode = {
+  def apply(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
     val hints = LazyModule(new TLHintHandler(supportManagers, supportClients, passthrough))
     hints.node := x
     hints.node

src/main/scala/uncore/tilelink2/Isolation.scala

@@ -0,0 +1,60 @@
+// See LICENSE for license details.
+
+package uncore.tilelink2
+
+import Chisel._
+import chisel3.internal.sourceinfo.SourceInfo
+
+class TLIsolation(f: UInt => UInt) extends LazyModule
+{
+  val node = TLAsyncIdentityNode()
+
+  lazy val module = new LazyModuleImp(this) {
+    val io = new Bundle {
+      val in  = node.bundleIn
+      val out = node.bundleOut
+    }
+
+    def ISO[T <: Data](x: T): T = x.fromBits(f(x.asUInt))
+
+    ((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
+
+      out.a.mem := ISO(in.a.mem)
+      out.a.widx := ISO(in.a.widx)
+      in.a.ridx := ISO(out.a.ridx)
+      out.d.ridx := ISO(in.d.ridx)
+      in.d.widx := ISO(out.d.widx)
+      in.d.mem := ISO(out.d.mem)
+
+      if (edgeOut.manager.base.anySupportAcquire && edgeOut.client.base.anySupportProbe) {
+        in.b.widx := ISO(out.b.widx)
+        in.c.ridx := ISO(out.c.ridx)
+        in.e.ridx := ISO(out.e.ridx)
+        out.b.ridx := ISO(in.b.ridx)
+        out.c.widx := ISO(in.c.widx)
+        out.e.widx := ISO(in.e.widx)
+        in.b.mem := ISO(out.b.mem)
+        out.c.mem := ISO(in.c.mem)
+        out.e.mem := ISO(in.e.mem)
+      } else {
+        in.b.widx := UInt(0)
+        in.c.ridx := UInt(0)
+        in.e.ridx := UInt(0)
+        out.b.ridx := UInt(0)
+        out.c.widx := UInt(0)
+        out.e.widx := UInt(0)
+      }
+    }
+  }
+}
+
+object TLIsolation
+{
+  // applied to the TL source node; y.node := TLIsolation()(x.node)
+  // f should insert an isolation gate between the input UInt and its result
+  def apply(f: UInt => UInt)(x: TLAsyncOutwardNode)(implicit sourceInfo: SourceInfo): TLAsyncOutwardNode = {
+    val iso = LazyModule(new TLIsolation(f))
+    iso.node := x
+    iso.node
+  }
+}

src/main/scala/uncore/tilelink2/WidthWidget.scala

@@ -176,7 +176,7 @@ class TLWidthWidget(innerBeatBytes: Int) extends LazyModule
 object TLWidthWidget
 {
   // applied to the TL source node; y.node := WidthWidget(x.node, 16)
-  def apply(innerBeatBytes: Int)(x: TLBaseNode)(implicit sourceInfo: SourceInfo): TLBaseNode = {
+  def apply(innerBeatBytes: Int)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
     val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
     widget.node := x
     widget.node

src/main/scala/uncore/tilelink2/package.scala

@@ -5,8 +5,9 @@ import chisel3.internal.sourceinfo.{SourceInfo, SourceLine, UnlocatableSourceInf
 
 package object tilelink2
 {
-  type TLBaseNode = SimpleNode[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
+  type TLOutwardNode = OutwardNode[TLClientPortParameters, TLManagerPortParameters, TLBundle]
-  type IntBaseNode = SimpleNode[IntSourcePortParameters, IntSinkPortParameters, IntEdge, IntEdge, Vec[Bool]]
+  type TLAsyncOutwardNode = OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]
+  type IntOutwardNode = OutwardNode[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
   def OH1ToUInt(x: UInt) = OHToUInt((x << 1 | UInt(1)) ^ x)
   def UIntToOH1(x: UInt, width: Int) = ~(SInt(-1, width=width).asUInt << x)(width-1, 0)
   def trailingZeros(x: Int) = if (x > 0) Some(log2Ceil(x & -x)) else None